FPGA RTL Design Engineer

Deven Prajapati

FPGA & RTL DESIGN ENGINEER

FPGA Engineer with experience in Verilog/SystemVerilog RTL design, AXI4-Stream interfaces, clock domain crossing and timing closure. Developed modules for Tachyon and Orthogone NICs, including multicast packet triggering, latency measurement, and AES- 256-GCM. Proficient in RTL simulation, timing analysis, hardware validation, and FPGA bring-up using Questa and XilinxVivado. TECHNICAL SKILLS

• FPGA & Tools - Vivado, Synthesis, Implementation, XDC Constraints, Timing Analysis, Basys-3.

• RTL Design: Verilog, SystemVerilog, FSM Design, Combinational & Sequential logic, Clock Divider.

• Verification: SystemVerilog, UVM, Assertions, RTL Simulation, Waveform Debugging.

• Protocols: AXI4, AXI4-Stream, AMBA AHB-Lite, SPI, PCIe, TCP/IP, UDP.

• Semiconductor Concepts: Setup/Hold time, STA basics, CDC(FIFO), CMOS logic, ASIC design flow.

• Scripting & Environment: Linux, Python, TCL.

WORK EXPERIENCE

1. Algowire Technologies Feb 2026 – Present

• Developed RTL modules for low-latency NIC applications, including packet generation, multicast packet triggering, AXI4-Stream interfaces, and FIFO-based clock domain crossing (CDC) for Tachyon and Orthogone NIC projects. Reduced packet processing latency through RTL pipelining and BRAM.

• Performed RTL simulation, waveform debugging, timing optimization, FPGA implementation, and hardware validation using Questa and Xilinx Vivado.

2. Silicon Interfaces Sep 2025 – Jan 2026

• Developed RTL modules in Verilog/SystemVerilog with functional testbenches, focusing on combinational and sequential logic, timing behavior, and functional correctness.

• Designed AMBA AHB-Lite Master interface modules in Verilog/SystemVerilog and verified functionality using UVM-based testbenches. Exposure to PCIe protocol fundamentals and SoC interface concepts. 3. SmartMark Feb 2025 – May 2025

• Conducted hardware-level debugging and verified board connectivity using JTAG to diagnose and resolve communication issues. Troubleshot signal integrity and system reliability to ensure stable hardware operation. 4. Network Techlab India Pvt. Ltd. Feb 2023 – June 2023

• Level 1 ESS Engineer. Conducted electrical and power-consumption audits, documented system efficiency, identified inefficiencies, and support low-power optimization decisions across multiple sites in India. 5. Power System Operation and Corporation (POSOCO) Feb 2022 – Jan 2023

• Graduate Apprentice Trainee.

PROJECTS

SPI Protocol: (PG - Diploma)

• Designed SPI master RTL in Verilog with clock divider, chip select, and serial data transfer logic.

• Verified functionality using a SystemVerilog testbench with simulation and waveform debugging.

• Implemented the design on FPGA using Xilinx Vivado and validated operation on hardware. AMBA AHB-Lite Master

• Designed an AMBA AHB-Lite master interface in Verilog with address, control, and data transfer logic.

• Implemented FSM-based protocol handling for single and burst transactions following AHB-Lite timing rules.

• Verified functionality using a UVM-based testbench with functional simulation and waveform debugging. ALU

• Designed parameterized ALU in SystemVerilog supporting diverse arithmetic, logical, and shift operations.

• Used SystemVerilog interface and modport to ensure modular design and structured signal connectivity.

• Verified functionality using a constrained-random SystemVerilog testbench. EDUCATION

• Post Graduation Diploma in VLSI (CDAC) 63.86% (2024)

• B.E. in Electrical Engineering (Mumbai University) 62.44% (2021)

• Diploma in Electrical Engineering (MSBTE) 65.45% (2018)

+91-771******* ****************@*****.*** Deven P. Mumbai, MH Deven

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