RTL Design Engineer

ROHIT KUMAR SINGH

RTL Design Engineer — FPGA Design/Verification — High-Speed Communication Systems

Email: **********@*****.*** Contact No.: +91-755******* LinkedIn: linkedin.com/in/rohit-singh-r4232 Current Loc.: Noida, India Professional Summary

• Results-driven RTL Design Engineer with 4.5+ years of experience in FPGA design and verification using Xilinx and Siemens EDA tools.

• Proficient in Verilog/VHDL for RTL development of complex digital and multi-clock domain systems.

• Hands-on experience with Xilinx Zynq-7000 and Zynq UltraScale+ MPSoC devices.

• Expertise in RTL coding, timing closure, CDC analysis, linting, synthesis support, and FPGA debugging using ILA.

• Strong understanding of SoC architecture, AXI, Ethernet, UART, SPI, I2C, HDMI, DDR3 and GTX-based interfaces.

• Skilled in RTL optimization, hardware debugging, and resource utilization improvement.

• Familiar with TCL and Python scripting for design automation and debugging. Technical Skills

HDL Languages Verilog, VHDL, SystemVerilog (Basic) FPGA Tools Vivado, ISE, QuestaSim, ModelSim

Protocols AXI4, AXI-Lite, Ethernet, UART, SPI, I2C, HDMI Memory DDR3, BRAM, FIFO

Platforms Artix-7, Zynq-7000, Zynq UltraScale+ MPSoC Verification CDC, Linting, Simulation, Debugging

Timing STA, Timing Closure, XDC Constraints

Scripting TCL, Python

Debug Tools ILA, Vivado Debugger, Oscilloscope

Professional Experience

Aujus Technology Pvt. Ltd.

Senior FPGA / RTL Design Engineer Oct 2021 – Present

• Worked on architecture-level design and development of FPGA/SoC-based digital systems for communication and signal processing applications.

• Designed and developed RTL code using Verilog/VHDL for complex digital blocks and multi-clock domain systems.

• Performed simulation-level testing and functional verification using ModelSim/QuestaSim.

• Designed FSM-based control logic and reset synchronization circuitry.

• Created and managed XDC timing constraints for FPGA designs.

• Conducted CDC checks, linting analysis, STA, timing closure and optimization activities.

• Worked on SoC integration involving AXI4/AXI-Lite, Ethernet, HDMI, SPI, I2C, UART, BRAM, FIFO and Xilinx IPs.

• Developed and integrated high-speed Ethernet interfaces including 1G Ethernet and GTX-based communication systems.

• Performed DDR3 memory bring-up, calibration support and hardware debugging using Vivado and ILA.

• Generated FPGA bitstreams and performed hardware validation on Artix-7, Zynq-7000 and Zynq UltraScale+ MPSoC platforms.

• Automated Vivado synthesis, implementation and bitstream generation flows using TCL scripting.

• Contributed to Ethernet Switch, IRIG-B Timing, HDMI Video Processing and FFT-based Signal Processing projects.

1

Internship / Training

PinE Training Academy

FPGA System Design Trainee Apr 2021 – Sep 2021

• Learned FPGA design flow including RTL design, simulation, synthesis, implementation and bitstream genera- tion.

• Developed and simulated Verilog/VHDL modules on Xilinx platforms.

• Performed functional verification using ModelSim.

• Worked on timing analysis, CDC concepts and FPGA implementation methodologies.

• Integrated UART, SPI and GPIO interfaces.

• Performed FPGA hardware validation using ILA.

Projects

1. Ethernet Switch 1G

Technology: Xilinx Vivado — Verilog/VHDL — FPGA: Artix-7

• Designed and implemented an 8-port 1G Ethernet Switch on Artix-7 FPGA using VHDL.

• Integrated Tri-Mode Ethernet MAC (TMAC) and PCS/PMA IP for Gigabit communication.

• Developed pipelined packet processing, MAC-based switching and BRAM-based buffering.

• Implemented CDC synchronization and achieved timing closure at 125 MHz. 2. Timing Dissemination Control Unit

Technology: Xilinx Vivado — Verilog/VHDL — Board: ZedBoard

• Developed a real-time countdown and timing dissemination system.

• Implemented IRIG-B synchronization and countdown timer control.

• Designed Ethernet-based time dissemination and display interfaces. 3. VD Hold Interface Unit (VD-HIU)

• Designed a remote HOLD UNIT to halt countdown timing in auto-launch systems.

• Enabled synchronized operation with a central base station server. 4. Time Stamp and Video Mixing Over High-Definition Video Technology: ZCU106 — Verilog/VHDL

• Designed a real-time FPGA-based video processing system supporting HDMI video up to 4K60p.

• Overlayed Ethernet-received timestamps onto live HDMI video streams.

• Developed configurable timestamp position, size and color rendering logic.

• Performed timing optimization and hardware validation using ILA. 5. Fourier Transform Infrared Spectroscopy (FT-IR) Technology: ZYBO Z20 — Verilog/VHDL

• Implemented FFT-based signal processing for FT-IR applications.

• Captured ADC samples at 200 kHz and streamed data at 125 MHz.

• Developed BRAM buffering, CDC handling and FFT integration.

• Optimized timing and resource utilization.

Education

B.Tech in Electronics & Communication Engineering

Dr. A.P.J. Abdul Kalam Technical University, Uttar Pradesh CGPA: 7.4/10 2016–2020

Additional Information

• Open to relocation for better career opportunities.

• Actively learning advanced FPGA design and verification methodologies. 2

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