| Resume alert | Resumes 61 - 70 of 454 |
Engineer Design
Santa Clara, CA
... Synthesis RTL code to gate-level netlist by Design Compiler, then check timing issue by Prime Time. Implementing an SAT Solver June - Auguest.2018 Python, minisat Design an SAT Solver that can determine a Boolean expression is evaluated to be satis ... - 2019 Nov 15
... Synthesis RTL code to gate-level netlist by Design Compiler, then check timing issue by Prime Time. Implementing an SAT Solver June - Auguest.2018 Python, minisat Design an SAT Solver that can determine a Boolean expression is evaluated to be satis ... - 2019 Nov 15
Software Engineer Electrical Engineering
San Jose, CA
... Online Education and Distance Learning Cadence Design Systems, 2002 – 2013 SMCS/Architect, Invented two-stage Clock Tree Synthesis (CTS) to effectively control clock skews and minimize buffering cost Revamped the CTS algorithm to consider clock gate ... - 2019 Sep 21
... Online Education and Distance Learning Cadence Design Systems, 2002 – 2013 SMCS/Architect, Invented two-stage Clock Tree Synthesis (CTS) to effectively control clock skews and minimize buffering cost Revamped the CTS algorithm to consider clock gate ... - 2019 Sep 21
Consultant,professor
Belmont, CA, 94002
... I have a Ph.D.in polymer chemistry from Leeds University,England;extensive experience in research & developments,mainly on synthesis,characterization & fabrication of polymeric materials to develop new polymer materials that will be used in various ... - 2019 Aug 30
... I have a Ph.D.in polymer chemistry from Leeds University,England;extensive experience in research & developments,mainly on synthesis,characterization & fabrication of polymeric materials to develop new polymer materials that will be used in various ... - 2019 Aug 30
Engineer Design
San Jose, CA
... § Languages: TCL, VHDL, C, C++, JAVA, HTML § Technical Competencies: Physical verification flow, ASIC Design Flow, FPGA Design Flow, Timing Analysis, Multiple clock domain design, RF system architecture design, RTL level design and synthesis, Test ... - 2019 Aug 27
... § Languages: TCL, VHDL, C, C++, JAVA, HTML § Technical Competencies: Physical verification flow, ASIC Design Flow, FPGA Design Flow, Timing Analysis, Multiple clock domain design, RF system architecture design, RTL level design and synthesis, Test ... - 2019 Aug 27
Engineer Electrical
San Jose, CA
... EDUCATION MS: Electrical Engineering (Dec 2018) San Jose State University (CA) B.Tech: Electrical and Electronics Engineering (2012) Uttar Pradesh Technical University (India) RELEVANT COURSES Digital System Design and Synthesis, ASIC CMOS Design, ... - 2019 May 14
... EDUCATION MS: Electrical Engineering (Dec 2018) San Jose State University (CA) B.Tech: Electrical and Electronics Engineering (2012) Uttar Pradesh Technical University (India) RELEVANT COURSES Digital System Design and Synthesis, ASIC CMOS Design, ... - 2019 May 14
Design Engineer Engineering
San Jose, CA, 95125
... These included: Multiple IP (ARM7, ARM9/ 11 Cortex, SPARC, DSP, Analog mixed signal IP cores) integration, benchmarking and SoC designs NPS Femto Satellite redesign Undersea LiDaR research and development Synthesis and Scan design regression, TRW, ... - 2019 Apr 28
... These included: Multiple IP (ARM7, ARM9/ 11 Cortex, SPARC, DSP, Analog mixed signal IP cores) integration, benchmarking and SoC designs NPS Femto Satellite redesign Undersea LiDaR research and development Synthesis and Scan design regression, TRW, ... - 2019 Apr 28
Electrical Engineering Design
San Jose, CA
... Performed logic synthesis and generated vector file consisted of data input and scan chain trace verification (DFT), applied gate level simulation and Timing Closure. Deployed Static Voltage Frequency Scaling (SVFS) to accomplish low power design. 8 ... - 2019 Apr 05
... Performed logic synthesis and generated vector file consisted of data input and scan chain trace verification (DFT), applied gate level simulation and Timing Closure. Deployed Static Voltage Frequency Scaling (SVFS) to accomplish low power design. 8 ... - 2019 Apr 05
Engineer Office
Mountain View, CA
... Achievements at the previous job: He developed a technology of mechano-activation synthesis for producing low-temperature thermoelectric triple alloys based on bismuth telluride and a switching alloy of nickel antimonide, developed an isolated argon ... - 2019 Mar 18
... Achievements at the previous job: He developed a technology of mechano-activation synthesis for producing low-temperature thermoelectric triple alloys based on bismuth telluride and a switching alloy of nickel antimonide, developed an isolated argon ... - 2019 Mar 18
Project Research
Milpitas, CA
... Lipids are a group of molecules that include fats and waxes, and they generally preserve better in sediments over long periods of time than molecules like DNA and protein SKILL SETS Chemistry Skills: Strong Peptide and Organic synthesis skills, air ... - 2019 Jan 06
... Lipids are a group of molecules that include fats and waxes, and they generally preserve better in sediments over long periods of time than molecules like DNA and protein SKILL SETS Chemistry Skills: Strong Peptide and Organic synthesis skills, air ... - 2019 Jan 06
Assistant Administrative
San Jose, CA
... CHOWDHURY (C) 408-***-**** ac7ore@r.postjobfree.com www.linkedin.com/in/chowdhuryfahima San Jose, CA QUALIFICATION SUMMARY Experienced in characterization, design, Gate-level simulation, synthesis and debugging RTL Design (Verilog) Hardware ... - 2018 Nov 13
... CHOWDHURY (C) 408-***-**** ac7ore@r.postjobfree.com www.linkedin.com/in/chowdhuryfahima San Jose, CA QUALIFICATION SUMMARY Experienced in characterization, design, Gate-level simulation, synthesis and debugging RTL Design (Verilog) Hardware ... - 2018 Nov 13