| Resume alert | Resumes 31 - 40 of 121 |
Nurse Nursing
San Jose, CA
... 2006-2007) 2004-2006 Consistent Second Honor Dean’s Lister (2nd Semester 2004- 1st Semester 2006) November 2006 “3rd Red Cross National Olympics: First Aid Olympics- Regional”-1st Runner-up Philippine National Red Cross Sta Cruz, Laguna March 2004 ... - 2018 Oct 09
... 2006-2007) 2004-2006 Consistent Second Honor Dean’s Lister (2nd Semester 2004- 1st Semester 2006) November 2006 “3rd Red Cross National Olympics: First Aid Olympics- Regional”-1st Runner-up Philippine National Red Cross Sta Cruz, Laguna March 2004 ... - 2018 Oct 09
Electrical Engineering Engineer
Fremont, CA
... Skills: Experience in Functional verification, Assertions, Functional Coverage, random-Constraint Testbench verification, Regression, CPU Architecture, Static Timing Analysis(STA), CMOS Circuits, FPGA Architecture, Cache memory, ASIC design flow - 2018 Aug 02
... Skills: Experience in Functional verification, Assertions, Functional Coverage, random-Constraint Testbench verification, Regression, CPU Architecture, Static Timing Analysis(STA), CMOS Circuits, FPGA Architecture, Cache memory, ASIC design flow - 2018 Aug 02
Design Electrical Engineering
San Jose, CA
... Skill, System Verilog, SystemC, UVM Design Tools Cadence (Virtuoso, Encounter, PSPICE), XILINX ISE Design suite, MATLAB, Simulink, Eagle, Git Experience with STA, RTL Design, ARM processors, Oscilloscope, Logic analyser, FPGA, ASIC Design, APB,SPI - 2018 Mar 29
... Skill, System Verilog, SystemC, UVM Design Tools Cadence (Virtuoso, Encounter, PSPICE), XILINX ISE Design suite, MATLAB, Simulink, Eagle, Git Experience with STA, RTL Design, ARM processors, Oscilloscope, Logic analyser, FPGA, ASIC Design, APB,SPI - 2018 Mar 29
Verilog, Perl, Digital IC design, FPGA/ASIC design, Physical Design
San Jose, CA
... • Implemented a high accuracy (1% error compare to Hspice simulation), memory efficient, multicore and multithreading supported STA model • The implemented algorithm is capable to work on both ASIC and special customized fabric which beyond the ... - 2018 Jan 11
... • Implemented a high accuracy (1% error compare to Hspice simulation), memory efficient, multicore and multithreading supported STA model • The implemented algorithm is capable to work on both ASIC and special customized fabric which beyond the ... - 2018 Jan 11
Design Engineer Professional Experience
San Jose, CA
... generation using ICC and Cadence Virtuoso, block-level and chip-level layout verification using ICV, Calibre and Redhawk, static timing analysis (STA) and timing closure, signal integrity, low power implementation, (LVS/DRC/ERC/ANT and LEC fixes). ... - 2017 Dec 21
... generation using ICC and Cadence Virtuoso, block-level and chip-level layout verification using ICV, Calibre and Redhawk, static timing analysis (STA) and timing closure, signal integrity, low power implementation, (LVS/DRC/ERC/ANT and LEC fixes). ... - 2017 Dec 21
Medical Technologist
Milpitas, CA, 95035
... and Treatment Program) Sta.Cruz, Metro Manila Position: Medical Technologist From July 2009 – present DUTIES AND RESPONSIBILITIES: TOXICOLOGY AND DRUG TESTING: Conduct Workplace Drug Testing Verifies the completeness of Chain of Custody Form. ... - 2017 Dec 19
... and Treatment Program) Sta.Cruz, Metro Manila Position: Medical Technologist From July 2009 – present DUTIES AND RESPONSIBILITIES: TOXICOLOGY AND DRUG TESTING: Conduct Workplace Drug Testing Verifies the completeness of Chain of Custody Form. ... - 2017 Dec 19
Design Electrical Engineering
San Jose, CA
... TECHNICAL SKILLS Skills:Hardware Design, VLSI, RTL coding, Static Timing Analysis (STA), Synthesis, Place and Route, DRC, LVS, PCB testing Hardware Languages: Verilog, System Verilog Lab equipment: MPLAB IDE, LTpower Play, multi-meter, Optical ... - 2017 Dec 06
... TECHNICAL SKILLS Skills:Hardware Design, VLSI, RTL coding, Static Timing Analysis (STA), Synthesis, Place and Route, DRC, LVS, PCB testing Hardware Languages: Verilog, System Verilog Lab equipment: MPLAB IDE, LTpower Play, multi-meter, Optical ... - 2017 Dec 06
Customer Service Representative
Livermore, CA
... EDUCATIONAL BACKGROUND: College: POLYTECHNIC UNIVERSITY OF THE PHILIPPINES Sta. Mesa, Manila, Philippines Bachelor in Broadcast Communication, May 2010 High School: TANAY NATIONAL HIGH SCHOOL Tanay, Rizal, Philippines, April 2006 Elementary: ILAYA ... - 2017 Nov 08
... EDUCATIONAL BACKGROUND: College: POLYTECHNIC UNIVERSITY OF THE PHILIPPINES Sta. Mesa, Manila, Philippines Bachelor in Broadcast Communication, May 2010 High School: TANAY NATIONAL HIGH SCHOOL Tanay, Rizal, Philippines, April 2006 Elementary: ILAYA ... - 2017 Nov 08
Staff Accountant
San Jose, CA
Charu Hirwe San Jose, CA 734-***-**** ac22yb@r.postjobfree.com Objective To join a nance team in a reputed organization with the skill set of a sta accountant. Education Bachelor’s in Advanced Accounting and Auditing University of Pune, India ... - 2017 Nov 01
Charu Hirwe San Jose, CA 734-***-**** ac22yb@r.postjobfree.com Objective To join a nance team in a reputed organization with the skill set of a sta accountant. Education Bachelor’s in Advanced Accounting and Auditing University of Pune, India ... - 2017 Nov 01
Project Data
Union City, CA
... Location Manila, Phil Duration May 2014 – Sep 2014 Project Sta.Ana Role BA Intern Roles & Responsibilities: Documented business workflows in UML diagrams (State diagrams) and forwarded them to stakeholders to review. Extensively involved in data ... - 2017 Oct 11
... Location Manila, Phil Duration May 2014 – Sep 2014 Project Sta.Ana Role BA Intern Roles & Responsibilities: Documented business workflows in UML diagrams (State diagrams) and forwarded them to stakeholders to review. Extensively involved in data ... - 2017 Oct 11