Design Electrical Engineering

Preetkiran Brar

Fremont, CA *****

Email: ac3mgt@r.postjobfree.com Phone: 510-***-****

Master of Science in Electrical Engineering Graduate specialized in ASIC Design. Hands on experience in board level test- ing, troubleshooting and circuit Debugging. Proficient in Verilog, logic design principles, Static Timing Analysis, SoC design methodology, verification, C and Scripting. Familiar with Analog/Digital Design methodology. Comfortable with transistor level design.

TECHNICAL SKILLS

Skills:Hardware Design, VLSI, RTL coding, Static Timing Analysis (STA), Synthesis, Place and Route, DRC, LVS, PCB testing Hardware Languages: Verilog, System Verilog

Lab equipment: MPLAB IDE, LTpower Play, multi-meter, Optical Spectrum analyzer, Logic analyzer Electronic Design Tools: Synopsys VCS, NCVerilog, Design Compiler, Altera Quartus II, Cadence Virtuoso, Cadence Encounter, Cadence Allegro Physical Viewer, ModelSim. Programming & Scripting: C, Python

Protocols: AHB, APB, UART, PCI, SPI, I2C

Networking Protocols: TCP/IP, DNS, DHCP, Routing Protocols, Switching, HTTP and SNMP. RELAVENT EXPERIENCE

Hardware Test Engineer, Cisco systems Inc. June 2017– Present

• Working in the PSG Group, responsible for Fabric cards & Route Processor board bring up

• Board Power off Visual Inspection

• Programming CAN Bus Controller, Power Sequencer and Firmware upgrade for IPU

• Boot FC and RP cards with diagnostics software and run full diag test suite

• Debug failures reported during bring up

• Proto-tracking and distribution

EDUCATION

San Jose State University May 2016

Masters of Science, Electrical Engineering

Related Coursework: ASIC CMOS Design, Advanced Computer Architecture, Digital System Design, Semiconductor Devices, Internetworking, Covergent Voice and Data Networks, SoC Design and Verification with System Verilog. Punjabi University, India May 2011

Bachelor of Engineering, Electronics & Communication PROJECTS

SoC Arbiter for a bus with 6 masters & 13 slaves using System Verilog (Synthesized using Synopsys DC)

• Designed a SoC arbitrator selecting Master based on probability given. Arbitration accurate to 99.5% achieved.

• Data in/out, Address in/out, Slave Read/Write handled. Arbitrator design related to AHB bus. Design 4 Bit Synchronous Counter Using Asynchronous Reset

• Designed 4 Bit up/down counter which performs either up or down counting using a synchronous clock.

• Corner Analysis performed to analyze the circuit behavior under different stress condition.

• Implemented the design using 45nm technology and layout of its submodule with clean DRC and LVS errors using the EDA tool (Cadence Virtuoso).

.Optimized 5th degree polynomial design for performance

• Static Timing Analysis, synthesis and Place-and-route performed on a Verilog code of pipelined design.

• Optimized the clock frequency by two levels (20MHz to 200MHz and 200MHz to 300MHz).

• Implemented the design using Verilog HDL, Synthesis performed with Synopsys Design Compiler. Design, optimize and analyze an 8-bit Scalar Processor

• Designed and optimized an 8-bit scalar processor using Finite State Machine and interfaced with 256 bytes of external memory. Processor performs simple arithmetic, read and copy instructions.

• Design was simulated and synthesized for 300MHz and timing reports were generated.

• Technologies: Verilog HDL, Synopsys Tools, Static Timing Analysis, Gate-Level Simulation (GLS). How to fix timing problem in ASIC CMOS Design (Study Paper)

• Several Problems related to ASIC Design like setup time violation, hold time violation, metastability, clock skew and minimum operating frequency are explained. Some methods to delay like pipelining, use of some special gates and logic, adjusting the number of Fan-In’s and Fan-Out’s and use of interconnections are suggested. WORK PERMIT: GREEN CARD

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