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Design Electrical Engineering

San Jose, CA
March 29, 2018

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**** ******* *****, *** ****, California 408-***-****


Seeking a job opportunity where I could leverage my strong VLSI design and verification skills. EDUCATION

Master of Science, Electrical Engineering DEC 2017 Colorado State University, Fort Collins, CO CGPA – 3.84 Bachelor of Technology, Electronics and Communication Engineering MAY 2015 Calicut University, Kerala, India CGPA – 3.9


Sensor Development Intern, CSU Energy Institute, Colorado FEB 2017 – AUG 2017

Developed hybrid methane sensing boards for natural gas transmission and storage systems.

Tested Nucleo boards by integrating with Beaglebone.

Performed calibration studies for the sensors and analysed information collected from test sites. Asst. Systems Engineer, Tata Consultancy Services, India AUG 2015 - DEC 2015

Coordinated conversion of COBOL-based financial software to JAVA with programming team.

Compiled decision logic, created a pseudo code for the programming team, and helped validating the source code.


8-bit Asynchronous Counter – Cadence Virtuoso & Encounter

Design was based on the TSMC 180nm process, and satisfied DRC, LVS, and QRC checks.

A supply voltage of 0.9 Volts was used and the timing spec of 1MHz was achieved.

Achieved a 40% reduction in layout size and minimized power consumption. Two-stage operational trans-conductance amplifier – Cadence Virtuoso

Design based on TSMC 90nm process, with a supply voltage of 1.2 Volts.

Achieved an intrinsic gain of 15dB with a minimised power consumption of 2.4 mW.

Obtained a steady state response up to 10MHz and a settling time of 1.6ns. Digital Delay Locked Loop – Xilinx Vivado, Verilog

Implemented an all-digital Delay Locked Loop on Be Micro Max10 FPGA Evaluation board.

Perfect lock-in scenarios achieved up to a frequency of 150 MHz Image Filtering – C, CUDA

Implemented Sobel, average & high boost filters to compare edge detection abilities on different images. The simulation was accomplished using NVIDIA Tesla M2070 GPU board.

A 10x speedup was achieved for Sobel filter in GPU cores against traditional CPU run.

An increase of 5x speedup was attained in GPU with an increase in kernel size. Roadside Air Quality Monitoring System – Python, OpenCV

Implemented an air quality monitoring system in one of the busy roads in the city of Fort Collins.

Classified the vehicles from the videos obtained and predicted the amount of emissions.

Compared the prediction with the actual value collected by an air pollution sensor. Dual Port RAM – System Verilog, UVM

Implemented the dual port RAM using Verilog independently.

Architected the class based verification environment using system Verilog and verified the module using UVM class based test bench.

Generated functional coverage for RTL verification. COURSEWORK

VLSI System Design Analog and Mixed MOS Circuits Digital System Design

Solid State Devices Computer Organisation & Architecture

Embedded Systems

Linear Integrated Circuits

Advanced Computer Architecture FPGA Signal Processing SKILLS

Programming C, C++, Verilog, CUDA, VHDL, Python, COBOL, TCL, Cadence Skill, System Verilog, SystemC, UVM Design Tools Cadence (Virtuoso, Encounter, PSPICE), XILINX ISE Design suite, MATLAB, Simulink, Eagle, Git Experience with STA, RTL Design, ARM processors, Oscilloscope, Logic analyser, FPGA, ASIC Design, APB,SPI

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