| Resume alert | Resumes 21 - 30 of 391 |
Layout Designer Design
San Jose, CA
... Analog Switch design used to Supply a Photodiode · Lead in design of SoC Layout (wafer of 5mm X 5mm) · Collaboration with FPGA designers on SoC layout checking · Collaboration with detector of deep space team · Expertise in Modeling of an extremely ... - 2023 Oct 23
... Analog Switch design used to Supply a Photodiode · Lead in design of SoC Layout (wafer of 5mm X 5mm) · Collaboration with FPGA designers on SoC layout checking · Collaboration with detector of deep space team · Expertise in Modeling of an extremely ... - 2023 Oct 23
Software Engineer C C++
San Jose, CA
... Modified BSP, firmware interface with FPGA. ·Network/USB Printer: Lead a team of engineers to design and develop a network printer firmware using VxWorks. Printer consists of TCP/IP off load NIC and USB. Developed NIC and USB device drivers using C. ... - 2023 Sep 29
... Modified BSP, firmware interface with FPGA. ·Network/USB Printer: Lead a team of engineers to design and develop a network printer firmware using VxWorks. Printer consists of TCP/IP off load NIC and USB. Developed NIC and USB device drivers using C. ... - 2023 Sep 29
Data Center Research
San Jose, CA
... Hardware counters and other support for profile guided optimizations, PCIe (PCI Express), Field Programmable Gate Arrays (FPGA), (Processor Specific) Application Binary Interface (psABI/ABI) for PowerPC and x86. Compilation Tools: Multiple families ... - 2023 Sep 21
... Hardware counters and other support for profile guided optimizations, PCIe (PCI Express), Field Programmable Gate Arrays (FPGA), (Processor Specific) Application Binary Interface (psABI/ABI) for PowerPC and x86. Compilation Tools: Multiple families ... - 2023 Sep 21
C++ Verification Engineer
San Mateo, CA
... Experience with FPGA SoC architectures of this MCF environment and discover with FPGA design to understand and report RTL bugs to development team. Used TREX command to configure loopback connectivity for the HESE I3C/I2C ports during runtime. The ... - 2023 Sep 21
... Experience with FPGA SoC architectures of this MCF environment and discover with FPGA design to understand and report RTL bugs to development team. Used TREX command to configure loopback connectivity for the HESE I3C/I2C ports during runtime. The ... - 2023 Sep 21
High Speed Hardware Engineer
Fremont, CA
... Hardware design, debug and transfer to manufacturing of very High Speed products, FPGA Boards with high speed interfaces, Server Motherboards, Switches, Embedded Processors x86 and Arm based Systems and Network Appliances Giga Bit, 3.125G,5Gig, 10 ... - 2023 Sep 08
... Hardware design, debug and transfer to manufacturing of very High Speed products, FPGA Boards with high speed interfaces, Server Motherboards, Switches, Embedded Processors x86 and Arm based Systems and Network Appliances Giga Bit, 3.125G,5Gig, 10 ... - 2023 Sep 08
Project Manager Software Development
Palo Alto, CA
... socket clients for fast/reliable TCP/IP transport, command parsers and GUI, FPGA control interface, GPU and data compression for high fidelity GUI. Microsoft, Redmond, WA 7/14/08-10/1/09 Program Manager/ScrumMaster specifically for WLAN Vendor ... - 2023 Aug 22
... socket clients for fast/reliable TCP/IP transport, command parsers and GUI, FPGA control interface, GPU and data compression for high fidelity GUI. Microsoft, Redmond, WA 7/14/08-10/1/09 Program Manager/ScrumMaster specifically for WLAN Vendor ... - 2023 Aug 22
Software Engineer C++
Santa Clara, CA
... Software Engineer Summary • Programming languages: C, GNU Assembly, GNU make, Python, C++, Bash script, Java, C#, Javascripts, • Hardware platform experiences: ARM, 8051, Mips, Xilinx FPGA • Software OS experience: Linux, uboot, Android, SELinux, ... - 2023 Aug 21
... Software Engineer Summary • Programming languages: C, GNU Assembly, GNU make, Python, C++, Bash script, Java, C#, Javascripts, • Hardware platform experiences: ARM, 8051, Mips, Xilinx FPGA • Software OS experience: Linux, uboot, Android, SELinux, ... - 2023 Aug 21
ASIC/SOC Architect/Lead
Livermore, CA
... right AIOT (Advanced IO Timing) model usage and IBIS-based board simulations, verifying critical FPGA and HC ASIC timing waveforms in Quartus and PrimeTime, EPE (Early Power Estimation) and final power computation including ODC (On-Die Capacitance). ... - 2023 Aug 15
... right AIOT (Advanced IO Timing) model usage and IBIS-based board simulations, verifying critical FPGA and HC ASIC timing waveforms in Quartus and PrimeTime, EPE (Early Power Estimation) and final power computation including ODC (On-Die Capacitance). ... - 2023 Aug 15
Design Engineer Controller
San Jose, CA
... SKILLS FPGA/ASIC Tools: Xilinx, Altera, Cadence, and Synopsys. DSP: wireless microwave, power control. Wireless: QAM and BPSK. Interface Protocols: Ethernet, TCP/IP, SONET, Flash Controllers, SATA, SAS, FC, FCoE, PCIe, USB, SMB, I2C, SPI, SDIO, NCSI ... - 2023 May 30
... SKILLS FPGA/ASIC Tools: Xilinx, Altera, Cadence, and Synopsys. DSP: wireless microwave, power control. Wireless: QAM and BPSK. Interface Protocols: Ethernet, TCP/IP, SONET, Flash Controllers, SATA, SAS, FC, FCoE, PCIe, USB, SMB, I2C, SPI, SDIO, NCSI ... - 2023 May 30
Computer Engineer
Santa Clara, CA
... Verilog, System Verilog(beginner), Perl(beginner), TCL(beginner) ● Data Structures & Algorithms, Object-Oriented Programming ● FPGA Design, MIPS Assembly Language, Computer Architecture ● Real-Time Embedded Systems (FreeRTOS), Serial Communication ... - 2023 May 24
... Verilog, System Verilog(beginner), Perl(beginner), TCL(beginner) ● Data Structures & Algorithms, Object-Oriented Programming ● FPGA Design, MIPS Assembly Language, Computer Architecture ● Real-Time Embedded Systems (FreeRTOS), Serial Communication ... - 2023 May 24