SREEKUMAR R. NAIR
**** ******* *****, *** ****, CA 95127
To pursue a challenging career in R&D and productization, of state-of-the-art technologies involving optimizations for cloud and data center solutions, low level system architectures, security, virtualization, dynamic binary translation, hardware/software co-design of processor (micro)architectures. Highlights
1. 34 years of experience in the computer industry - 30+ years in the areas of low-level platform architectures, various realms of virtualization (process, processor, system/OS, discrete devices including graphics and networking), dynamic binary translation, static and dynamic compiler optimizations, (micro)architecture optimizations with specific focus on multi-core architectures, and security.
2. Founder, Chief Technology Officer, and Principal Developer at Dynavisor, Inc., a Silicon Valley startup company leading innovations and delivering state-of-the-art data center acceleration solutions. I am the Chief Architect of the key product, TorrentPro, that transparently accelerates the storage and network data of large real-world applications resulting in their running up to 10x faster
(without any changes to the applications or the operating system) and saving up to 80% of cost for deploying applications in the cloud and data centers. TorrentPro™ is the heart of Dynavisor’s vision,
“Bringing Supercomputing to the Masses”. The primary customer base includes multiple sites in the US Government and Department of Defense, US National Institutes of Health, leading banks, etc. Dynavisor technology is protected by twenty patents, thirteen of which are already issued, and the rest are in the late stages of defense with USPTO. 3. Strong hands-on knowledge of the data center and the cloud - from bringing up data centers from the ground up to performance debugging and optimization of data centers. Firsthand experience configuring and optimizing public cloud infrastructures to best suite deployment of each type of applications as well as handholding through migration to public clouds. 4. Thirty-Four (34) patents: Twenty-One (21) awarded, Eight (8) published, and Five (5) in flight, spanning the areas of virtualization (processor, system, device, I/O, information, storage), dynamic translation, microarchitecture features to aid runtime optimizations, classical compiler optimizations, static/dynamic binary optimizations, compiler techniques for controlled speculative execution, dynamic I/O scaling, security of I/O virtualization. 5. Strong technical expertise spanning various software technologies targeting: Passive Device Virtualization, Processor virtualization (system level dynamic translator for ISA virtualization, hardware/software co-designed (micro)architectures), Memory Virtualization, Network/Device Virtualization, Micro-op optimizations, System virtualization (VMware ESX, Intel Virtx2, QEMU), System/Processor/Process level dynamic binary translation, Architectures for CPU, Memory, and I/O Virtualization (Intel VT-x/EPT/VT-d, AMD SVM/NPT/IOMMU), Security architectures (Intel TXT, AMD SVM), Microarchitecture optimizations (multi-core, runtime optimizations), Processor
(micro)architectures (x86, ARM, SPARC, PowerPC), Runtime optimizations (.NET, Java), Embedded and low level system internals, Classical compiler construction, Operating systems internals (Linux, Windows CE, Windows Mobile, AT&T Unix SVR4). 6. Strong skills to lead both cutting-edge research as well as fast down-to-earth productization of state- of-the-art technologies.
7. Strong skills in the areas of project management, team leadership, mentoring, analytical and communication skills.
Expert Level: C/C++/C#
Proficiency: Java, Pascal, Python, Perl, SQL, COBOL, Shell Scripts, HTML Kernel Programming:
Operating Systems: Drivers and Modules on Microsoft Windows, BSD, FreeBSD, Solaris, Unix SVR4, Linux
Virtualization: VMware ESXi, Linux Kernel Virtual Machine (KVM), Xen, Virtual Box Containers: LXC/LXD
Hardware Virtual Machine, Intel Virtualization Technology (VT-x/VT-d), AMD Secure Virtual Machine (AMD-V/SVM), Instruction Set Architectures (Intel/AMD x86, PowerPC, Motorola 68K, MIPS, SPARC, ARM/Graviton), Microarchitecture, Micro-ops, System Architecture, Compute Express Link (CXL), System-on-Chip (SoC), Intel Trusted Execution Technology
(TXT). Hardware counters and other support for profile guided optimizations, PCIe (PCI Express), Field Programmable Gate Arrays (FPGA), (Processor Specific) Application Binary Interface (psABI/ABI) for PowerPC and x86.
Multiple families of compilers, profilers, debuggers, performance analysis tools. Microsoft Windows: Visual Studio suite
Unix (Solaris, SVR4): cc, prof/gprof, dbx
Linux: gcc, gprof, gdb, perf (based on performance counters) Embedded compilation tool suites from Microtec Research and Ready Systems, MetaWare, Green Hills, Wind River, SDS, etc.
Debugging live programs, executables, analyzing core files and crash dumps. Hands-on experience in the following commercial software: VMware ESXi Hypervisor [Intel, AMD], Microsoft .NET JIT Compiler [Intel], Sun SPARC Compiler [Sun], MetaWare Embedded PowerPC Toolchain [MetaWare], Microtec Compilers
[Microtec], MIPS RISCompiler [Tandem, Wipro], Unix System V Release 4 (SVR4) Tandem Fault-tolerant Kernel [Tandem, Wipro]
Software products built from the ground up:
Dynavisor I/O Virtualization (DIOV) technology, System level dynamic translator, Dynamic, Processor Translator [Intel], Micro-op optimizer [Intel], Post-optimizer, a link-time optimizer
Hands-on experience in the following opensource software: Linux Operating System: Kernel, Modules/Drivers, Solaris Operating System, Xen Hypervisor, Linux Kernel Virtual Machine (KVM) Hypervisor, QEMU Dynamic Translator and Virtualization Framework, Microsoft Device Emulator, OpenStack cloud computing platform
Amazon Web Services (AWS), Microsoft Azure, Google Cloud Platform (GCP), Oracle Cloud Infrastructure (OCI): Management consoles, APIs, application suites, managed services, storage architectures, CLI, Infrastructure as Code (IaS), Experience Summary:
1. Consulting Services 
2. Dynavisor Inc: Founder and CTO [September 2012 till Date] 3. Nokia Research Center: Principal Scientist [April 2010 till September 2012] 4. Advanced Micro Devices: Senior Member of Technical Staff [July 2009 till April 2010] 5. Phoenix Technologies Limited: Software Architect [January 2009 till July 2009] 6. MobileIron, Inc: Virtualization Architect [June 2008 till January 2009] 7. Intel Corporation: Senior Research Scientist, Senior Staff SW Engineer [April 2004 till June 2008] 8. Sun Microsystems: Staff Engineer [March 1997 till April 2004] 9. MetaWare Inc: Software Engineer [October 1995 till February 1997] 10. Microtec Research Inc: Software Engineer [June 1994 till October 1995] 11. Wipro Infotech Limited: Senior Engineer (SW, R&D) [Jan 1989 till May 1995] Areas of Technology: Summary
Data Center & Cloud Optimizations
Areas of Technology: In Detail
Data Center & Cloud Optimizations:
1. Dynavisor Inc:
a. Implemented Dynamic I/O virtualization (DIOV), on FreeBSD hypervisor (Bhyve) to enable guest OS processes to share the same memory address space with the hypervisor to perform accelerated I/O operations on host devices like storage, networking, and graphics. This resulted in up to 10x speedup of applications in the guest operating system without any changes to the applications or the operating system. Later extended the support to other Linux hypervisor platforms like KVM and Xen.
b. Implemented Linux kernel-mode drivers (block drivers and filesystem drivers) to manage storage over a distributed parallel hyper-converged, multi-cloud storage architecture for accelerating (a) on-node, (b) east-west and (c) north-south data movements in cross geo data centers. The storage was partitioned into physically isolated planes to enable secure multi-tenant deployments. Another important feature included massive parallelism in the flow of data between nodes in a cluster as well as between clusters across clouds. This was termed, “Hyperconvergence of the Cloud.”
c. Architected Accelerated Edge Computing. The high data throughput enabled by TorrentPro™ enables intensive processing of data at source (more computing pushed to the edge), thereby (a) improving aggregate compute throughput across wide clusters on the edge, (b) transferring richer (and less voluminous) data to the backend data centers, (c) reducing the stress of centralized data processing in the backend data centers, and (d) optimizing the network bandwidth usage between the edge and the backend data centers. d. Architected Smart Cloud Migration. This feature enables existing customers on public clouds (Amazon Web Services, Microsoft Azure, Google Cloud Platform, etc.) to efficiently migrate to other clouds with minimal data egress costs. TorrentPro™ provides a transparent data bridge between the clouds through which cross-cloud data migration (egress) happens on demand. This also enables instant cloud migration since you do not have to wait for all of the data to complete migration before you start deploying your applications on the new cloud.
e. Architected cloud brokerage and service automation layers (Dynavisor IaC - Infrastructure as Code) involving Openstack for on-premise data centers, and the command line interfaces
(CLI) from public clouds (Amazon Web Services, Microsoft Azure, Google Cloud Platform, etc.) to build a GUI based Canvas to facilitate configuration of large hyperconverged or storage clusters, automatically procuring compute, storage, and networking resources from public cloud and automatically building high efficiency cloud clusters out of mid-range cloud components bringing dramatic cost savings to customers. f. Currently architecting hardware assisted coherency management for the next generation superscalar storage architecture using Computer Express Link (CXL) – full hardware support expected in 2024.
g. Currently working with Intel to deploy their FPGA and IPU (Infrastructure Processing Unit) to accelerate coherence, encryption, compression, TCP offloading, multicasting, and network acceleration.
h. Currently designing an add-on PCIe (PCI Express) card to embody the storage acceleration solution, potentially using FPGA for accelerating specific algorithms. Virtualization:
This section covers all my experience in the areas of system virtualization, OS virtualization
(Containerization), Processor Virtualization, etc. 1. Consulting Services:
a. Vultr, a Tier 3 cloud provider, experienced a problem in KVM hypervisor pursuant to upgrade to Linux 5.19 whereby the guest OS locked up because of an integer overflow in the EPT page fault handler. I wrote a kernel function instrumentation (KFI) module for KVM hypervisor to non-intrusively analyze the physical memory accesses at each EPT violation and helped to debug the problem. I delivered a host kernel patch to reproduce the problem in a few minutes (used to take days for the lockup to occur). b. Amazon Web Services (AWS) partnering with SAP aims at accelerating Linux OS booting an SAP proprietary Type 1 hypervisor on top of AWS Graviton/Nitro hypervisor. This involved the profiling of Linus OS using QEMU system emulator, identifying hotspots in Linux OS using perf (hardware performance counter-based profiler), designing paravirtualization patches to bypass complex hotspots in the Linux kernel by availing of the services (hypercalls) offered by the SAP hypervisor. 2. Dynavisor Inc:
a. Please refer to the section on “Data Center & Cloud Optimizations” for the design and implementation of Dynamic I/O Virtualization on FreeBSD hypervisor, Bhyve. 3. Nokia Research Center:
a. Invented and prototyped “Devirtualization”, a technology for guest device drivers to directly call host device driver services of the hypervisor to enable guest applications in virtualization platforms to avail themselves of native speeds of host devices via a virtual file system (VFS) bridge across the guest and host operating systems. Collaborated with Rice University faculty and students to turn this into many successful publications. This served as Ph.D. topic for many graduate students. This was a forerunner of the Dynavisor technology. b. Co-architected a hardware-based virtualization solution to run multiple operating systems on the same mobile device. Implemented many software virtualization solutions including the sharing of devices like USB across multiple computers in a SoC (System on Chip). 4. Advanced Micro Devices (AMD):
a. Led the AMD engineering tactical relationship with VMware. Responsible for enabling AMD processor (micro)architecture features in VMware hypervisors to benefit performance, virtualization, security, and power management.
a. Architected the virtualization platform for mobile operating systems on MobileIron's mobile device management software stack. Successfully demonstrated that unmodified Windows Mobile OS images can be booted on QEMU system emulator (ARMv4/WindowsMobile to x86/Linux binary translation).
6. Intel Corporation:
a. DPT (Dynamic Processor Translator) is a software only Processor Virtualization technology for Intel IA-32 many core architectures. DPT comprises of a thin software layer which boots up on the processors, and “hides” the implementation of the hardware processor architecture from the various software components that run on the system. The low-level instruction streams that execute on the processor cores are intercepted by DPT and are dynamically translated, unbeknownst to the processors and the software components that originated the instruction steams, to render support needed for a variety of applications – like enabling research and product development in the areas of hardware/software co- designed architectures, reliability, security, and power management. The unique physical address based shared code cache architecture enabled reuse of 95% to 98% of translations across multiple address spaces.
b. As a member of the team interfacing with VMware, I was responsible for identifying architecture features in Intel processors targeting performance and virtualization. Optimized iSCSI CRC computation by 18.6x, demonstrated Dynamic Root of Trust for Measurement of ESX hypervisor, software emulation to supplement paging (memory virtualization) architecture features for fast OS migration. Brought up ESXi hypervisor on engineering versions of Intel motherboards, debugged multiple problems using crash dump analysis and provided fixes in vmkernel and drivers.
This section includes all my experience in the areas of Firmware, Operating Systems, Kernel and Device Drivers
1. Dynavisor Inc:
a. Please refer to the section on “Data Center & Cloud Optimizations” for the design and implementation of:
1. Dynamic I/O Virtualization which involved orchestration of virtualization infrastructures together with memory and process management interfaces of Linux OS. 2. The filesystem and block device drivers to accelerate storage over a wide area network. 3. Adapting Compute Express Link (CXL) to enhance coherence architecture. 4. Adapting Intel FPGA and IPU accelerators to enhance the performance of Dynavisor’s storage acceleration solution.
5. Embodying storage acceleration solution as a PCIe card with potential FPGA acceleration.
2. Nokia Research Center:
a. Please refer to the section on “Virtualization” for the design and implementation of: 1. Devirtualization, which implemented a virtual file system (VFS) bridge to enable guest applications to directly control devices on the host via host native device drivers. 2. Hardware based virtualization solution to run two operating systems on multiple CPUs in a System-on-Chip (SoC) architecture.
b. Developed Windows 8 device drivers to implement many new user experience in Nokia’s mobile device prototypes. These involved prototyping of hardware/software codesigned features (including drivers) involving depth camera, out-of-band remote kill, single hand hold controls for trackpad/microkeyboard, etc.
3. Advanced Micro Devices (AMD):
a. Implemented Secure Boot of VMware ESXi vmkernel based on TBOOT (same as the work I did at Intel – please see below).
4. Intel Corporation:
a. Please refer to the section on “Virtualization” for the design and implementation of: 1. Dynamic Processor Virtualization which booted a system dynamic translator on a baremetal motherboard.
2. Secure Boot (Dynamic Root of Trust of Measurement) of VMware ESXi vmkernel using TBOOT (Trusted Boot) using Intel TXT (Trusted Execution Technology) and TPM
(Trusted Platform Module).
3. Multiple optimizations in VMware ESXi vmkernel: 1. Hardware assisted iSCSI CRC computation.
2. Software simulation of access/dirty bits in Intel EPT (Extended Page Table). 4. Brought up ESXi hypervisor on engineering versions of Intel motherboards, debugged multiple problems using crash dump analysis and provided fixes in vmkernel and drivers.
b. Please refer to the section on “Compiler Optimizations” for the work on hardware assisted profile guided optimization. This phase involved the debugging and integration of device drivers to control the low latency traps initiated by the hardware. 5. MobileIron:
a. Please refer to the section on “Virtualization” for the bringup of an unmodified ARM-v4 mobile phone OS (ROM) image including all device drivers on an emulated (virtual) hardware.
6. Phoenix Technologies:
a. Successfully restructured the next generation source architecture for HyperSpace – significantly improving platform coverage, boot time, network connection speeds, power consumption on a NetBook hardware. This phase involved the bringup, debugging and tuning of drivers for all devices on the machine.
7. MetaWare Inc:
a. Please refer to the section on “Compiler Optimizations” for details about my work on embedded compiler toolchains and representing the company at Standards Committes. 8. Microtec Research:
a. Please refer to the section on “Compiler Optimizatiions” for details about my work on the embedded compiler toolchains.
9. Wipro Infotech Ltd:
a. Porting and sustenance of AT&T Unix (System V Release 4) on Tandem's fault tolerant NonStop Unix machine. Co-implemented a pseudo filesystem, /config, which worked with a graphical user interface to control all components on the machine – including CPUs, Memory, Mass Storage Cabinet, Network Switches, etc. Microarchitecture:
This section comprises of multiple projects I implemented on functional and cycle-accurate simulators of microprocessors to demonstrate the viability and performance opportunities of various microarchitecture features:
1. Intel Corporation:
a. Dynamic μOp (Micro-op) Optimizer: dynamic binary optimizer targeted for optimization of μOps in a many core simulation environment. The highlights of the μOp optimizer included a very fast, constant cost, highly scalable and parallel SSA engine, an analysis engine, and an optimization engine capable of performing various levels of optimizations. Involved major changes to cycle accurate simulators to demonstrate performance opportunities from the μOps optimizations.
2. Sun Microsystems:
a. Research prototype of a dynamic translation based Runtime Optimizer for the SPARC/Solaris platform which targeted simulators for future SPARC/Solaris platforms and performed speculative optimizations like run-ahead speculative thread generation employing runtime compilation techniques exploiting dynamic profile feedback. Demonstrated excellent performance improvement on important commercial applications using software run-ahead speculative threading. Involved major changes to cycle accurate simulator for an out-of- order processor to demonstrate this feature.
b. Researched and prototyped multiple microarchitectures for improving the efficiency of dynamic translation and runtime compiler optimizations: i. Using value speculation to break constraining dependencies in iterative control flow structures.
ii. Software value prediction using pendency records of predicted prefetch values iii. Monitoring pollution and prefetches due to speculative accesses iv. Hardware assisted control redirection of original computer code to transformed code v. Using address space bridge in postoptimizer to route indirect calls at runtime. Compiler Optimizations:
1. Intel Corporation:
a. Hardware Counter Based Light Weight Profiling Guided Continuous Optimization Framework implemented in one of the most popular managed runtime compilers in the industry. The optimizations aimed at improving memory level parallelism (speculative prefetch insertion), and reducing branch misprediction penalties like (speculative conditional branch predication) etc.
b. Implemented a Region Optimizer in Intel's StarDBT Dynamic Binary Translator – which performed architecture independent optimizations based on a query engine. 2. Sun Microsystems:
a. Static link time optimizer product for SPARC/Solaris platform to perform whole program optimizations like instruction cache line coloring, partial dead code elimination etc. I was responsible for evangelizing the technology, designing the end-to-end solution for the link- time optimizer, working with Systems Architecture Council (SAC, which is the governing body for technical designs) to obtain design approval, and with productization teams to define product specifications.
b. As member of SPARC Optimizing Code Generator Team, implemented various optimizations: Notable ones being peephole optimizations for speeding interval arithmetic
(7x), optimized exception handling for native Java and C++, prototype COMDAT method for link time instantiation of C++ template methods.
3. MetaWare Inc:
a. Project Lead for the entire MetaWare Embedded PowerPC Toolchain (compilers, assemblers, linkers, libraries, debuggers, profilers). The products spanned offerings on multiple Real Time Operating Systems and PowerPC boards. I was responsible for the full stack of operations from design, development, and testing/debugging of all components above the board and below the applications. Managed multiple large OEM accounts which integrated MetaWare Embedded PowerPC Toolchains into their end user product lifecycle. Familiarized with real time operating systems (RTOS) and debuggers from multiple vendors like Green Hills, Wind River, SDS, etc.
b. Represented MetaWare at the Embedded PowerPC ABI/EABI Standards Committees. 4. Microtec Research:
a. Responsible for various enhancements to multiple embedded toolchain components
(compilers, assemblers, linkers, debuggers) targeting Motorola 68K, x86. In particular, implemented a dynamic linker for Chorus Operating System. Optimizations to dramatically speed up link time and reduce object size. Prototype ELF assembler for Native Solaris Toolkit. The projects involved the bringup of applications on embedded boards from the operating system upwards. Familiarized with their flagship products, VRTX RTOS and X-ray debugger.
5. Wipro Infotech Ltd:
a. Porting and sustenance of MIPS RISCompiler at Tandem Corporation, as part of the integrated bringup of Tandem NonStop fault-tolerant kernel on Unix System 5 Release 4
1. US9081703B2: Nokia Research Center “Methods and apparatuses for facilitating sharing device connections”
2. US6654952B1: Sun Microsystems “Region based optimizations using data dependence graphs” 3. US7007271B2: Sun Microsystems “Method and apparatus for integrated instruction scheduling and register allocation in a postoptimizer”
4. US6751792B1: Sun Microsystems “Using value-expression graphs for data-flow optimizations” 5. US7185323B2: Sun Microsystems “Using value speculation to break constraining dependencies in iterative control flow structures”
6. US7353503B2: Sun Microsystems “Efficient dead code elimination” 7. US7472256B1: Sun Microsystems “Software value prediction using pendency records of predicted prefetch values”
8. US7124254B2: Sun Microsystems “Method and structure for monitoring pollution and prefetches due to speculative accesses”
9. US 9,384,024: Dynavisor [US14/133,396] “Dynamic Device Virtualization ” 10. US 10,514,938: Dynavisor [US14/133,419] “Dynamic Device Virtualization ” 11. US 9,910,689: Dynavisor [US14/555,473] “Dynamic single root I/O virtualization (SR-IOV) processes system calls request to devices attached to host” 12. US 10,635,469: Dynavisor [US16/128,913] “Dynamic I/O Virtualization [Continuation] System having Guest Memory Management”
13. US 10,031,767: Dynavisor [US14/631,731] “Dynamic Information Virtualization 14. US 10,255,087: Dynavisor [US15/880,092] “Dynamic I/O virtualization system having a bidirectional extended hybrid address space (EHAS) for allowing host kernel to access guest memory”
15. US 10,896,129: Dynavisor [US16/057,689] “Dynamic Storage Virtualization” 16. US 10,929,195: Dynavisor [US16/057,675] “Dynamic Cloud Virtualization” 17. US 10,977,061: Dynavisor [US14/133,443] “Dynamic Device Virtualization ” 18. US 11,175,936: Dynavisor [US16/744,773] “Dynamic I/O Virtualization [Continuation]” 19. Allowed: Dynavisor [US17/377,058] “Method and System for Dynamic Storage Scaling” 20. US US20210255882A1: Dynavisor [US17/227,960] “Dynamic Device Virtualization for use by Guest User Processes Based on Observed Behaviors of Native Device Drivers [Continuation]” 21. US20180341503A1: Dynavisor [US16/039,143] “Dynamic Information Virtualization
1. US20130055254A1: Nokia Research Center “Methods and apparatuses for providing a virtual machine with dynamic assignment of a physical hardware resource” 2. US20130204924A1: Nokia Research Center “Methods and apparatuses for providing application level device transparency via device devirtualization” 3. US20080244538A1: Intel “Multi-core processor virtualization based on dynamic binary translation”
4. US20090125894A1: Intel “Highly scalable parallel static single assignment for dynamic optimization on many core architectures”
5. US20040122800A1: Sun Microsystems “Method and apparatus for hardware assisted control redirection of original computer code to transformed code” 6. US20040045018A1: Sun Microsystems “Using address space bridge in postoptimizer to route indirect calls at runtime”
7. US20210133104A1: Dynavisor [US17/144,612] “Method and System for Storage Virtualization
8. US20210157653A1: Dynavisor [US17/167,969] “Method and System for Cloud Virtualization
1. Non-Provisional: Dynavisor [US17/518,859] “Dynamic I/O Virtualization Application Programming Interface”
2. Non-Provisional: Dynavisor [US17/518,863] “Security of Dynamic I/O Virtualization” Note: * - First inventor, ** - Second inventor
Publications and Submissions
1. Making I/O Virtualization Easy with Device Files, Published in: Technical Report 2013-04-13, Rice University (with other authors)
2. A Dynamic Processor Translator With Sharing Translations Across Multiple Address Spaces: Published in: Intel Dynamic Execution Environments Summit 2007 (with other authors) – now targeting external conferences.
3. StarDBT: An Efficient Multi-platform Dynamic Binary Translation System, Published in: The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007) (with other authors) 4. Entropy-Based Profile Characterization and Classification for Automatic Profile Management, Published in: The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007)
(with other authors)
5. Expanding Scope of Dynamic Register Liveness Analysis in Optimizing Binary Translators, submitted to Code Generation and Optimization (CGO) Workshop of Software Tools for Many Core Systems (STMCS) 2006 (with other authors)
6. <Paper based on the Hardware Counter Based Continuous Profile Guided Optimizations>, submitted to 3rd Intel Programming Systems Conference on Parallel Computing 2005 (with other authors).
7. Attributing Prefetching and Polluting Effects in Multi-Level Cache Systems, submitted to International Conference on Supercomputing (ICS) 2003 (with other authors). 8. PostOptimizer, A Link-Time Optimizer: Published in: SunTech 2001 Conference, Sun Microsystems Inc. (with other authors)
Bachelor of Technology in Computer Science and Engineering (BSCS), College of Engineering, Trivandrum, University of Kerala, India. November 1988 (Passed with Distinction). Academic Recognitions
1. Chicago Chapter Scholarship for being the highest-ranking incoming scholar in College of Engineering, Trivandrum, India, for the year 1984-'85 based on marks obtained in the Pre Degree examination. I ranked 27th in the state for the Engineering Entrance Examination. 2. National Merit Scholarship (Government of India) for ranking high in the statewide Secondary School Leaving Certificate (SSLC) Examination (Matriculation). I ranked 25th.