Muhammad Abbas

Cell: 510-***-**** adyynp@r.postjobfree.com https://www.linkedin.com/in/mabbas72/

Summary of Exeprience:

Technical Leadership:

•Led tape-outs across multiple process nodes (5nm, 7nm, 10nm, 14nm, 16nm, and 20nm) overseeing designs from RTL to GDSII.

•Executed physical implementation for high-speed and large/complex SoCs (>100M gates, GHz+, 30+ tapeouts) including floorplanning, CTS, PnR, and STA.

Design Expertise:

•Proven skills in full-chip integration, RTL development, SDC constraints, Liberty NLDM/CCS, and NDM model development for blocks.

•Experience integrating multiple third-party IPs at the SOC level.

•Extensive knowledge in microarchitecture, datapath block design, high-speed structured cell design, and semi-custom design (GHz+).

Low-Power Design:

•Proficient in implementing low-power UPF methodologies for synthesis, PnR, and DV.

•Extensive experience in power estimation/analysis at the RTL/gate-level for design optimization and achieving the best PPA.

Signal Integrity and Timing Analysis:

•Skilled in utilizing SI/STA tools and design methodologies like MCMM/DMSA with methods such as OCV/AOCV/SBOCV/POCV for ASIC signoff.

Reliability Verification:

•Well-versed in conducting Thermal, Signal EM, Power EM, Static IR drop & DVD analysis.

Design-for-Test (DFT):

•Expertise in DFT methodologies for scan/membist and test planning.

Tool Proficiency:

•Proficient in System Verilog/Verilog/VHDL/TCL/Python and various tools such as Synopsys, Cadence, Altera/Intel, Xilinx, and Mentor Graphics.

•Proficient in using EDA tools including Genus/DC, Innovus/ICC2/FC, Voltus/Redhawk/Totem, Tempus/PrimeTime, and Calibre/ICVfor design sign-off.

PCIe System Design:

•Experience in designing PCIe-based systems spanning from sub-system to ASIC to systems.

Project Management and Design:

•Over 25 years of hands-on experience in project and people management, design, and debug.

•Expertise in resource planning, assessing timelines for ASIC RTL freeze & final netlist, finalized package bump plan, and system layout freezing.

•Supervised document creation and doc management of various ASIC sub-systems using Confluence

SOC Architecture and Collaboration:

•Experienced SOC architect skilled at collaborating across RTL, PD, DFT, Verification, and Validation teams.

•Proficient in planning, negotiating, and establishing project milestones.

Publications:

•Notable author and presenter of top papers at LSI Logic, Synopsys, and Intel.

•Best paper award winner at 2017 IPPTC (Intel PSG Penang Technical Colloquium) on FIHM (Flat Implementation Hierarchical Modeling).

EXPERIENCE:

Chip Lead, Cornami Inc., CA [Nov 2019 – June 2023 ]

•Designed a massively parallel and highly scalable AI chip architecture with 2000+ cores having 300M+ logic gates on a 16nm die. This included ARM, HBM memory and HSIO interfaces for PCIe, Ethernet and Interlaken/CI.

•Drove the tile uArchitecture, RTL coding using System verilog, sdc constraints development, UPF implementation and hierarchical synthesis.

•Did chiplets and chip-level integration, hierarchical floorplanning, physical synthesis, low-power UPF, DFT, PnR, LEC, STA, and RV of the above design. This also included top-down synthesis, block-level lint, CDC runs, LEC, timing closure and timing model generation for each block.

•As an SOC lead, I also work with each team member to understand their challenges, debug and resolve their design & tools issues.

•Coordinate cross-functional work with RTL, PD, DFT, Verification and Validation teams, plan, negotiate and set overall project milestones.

•Work with IP vendors to define their tasks, set their deliverables/timelines and perform IP blocks integration into the SOC.

•Work with foundry on metal-stack selection, scribe-lines/seal ring specifications for single-die/multiple dies in a package, and resolve/converge on COWOS design details.

•Work with packaging on bump planning, c4 bumps, ubumps/probe pad orientation, silicon interposer, chiplets interconnects, SiP substrate, HBM2 DRAM/HardPhy, and SERDES Phy placement.

•Work with upper management and provide them with a weekly status report, next-week’s goals, current issues and their resolution, and feedback on strategic planning.

Senior Principal Consultant, Physical Design, Microsoft Corporation, CA [Aug 2020 – Jan 2022]

•Involved in the tapeout of latest Hololens design at TSMC 7nm and 5nm nodes.

•My primary responsibilities included synthesis, STA, static IR drop, dynamic voltage drop and power-EM/signal-EM analysis.

•Worked on the IR Drop analysis of the analog cores using SPICE, GDSII, Liberty, VCD and config files approach to generate their models at different levels of abstraction.

•Ran DVD analysis in Redhawk using the totem generated models for the analoig cores in a mixed-signal design environment.

•Developed an ECO methodology to capture worst DVD violators across different channels (even, odd and checkerboard odd), read it into PT-STA with voltage drop consideration and timing derates, and generate eco files to be read into ICC2.

•Earlier performed STA across the integrated digital and analog domain using Synopsys FC-CC-PTSTA (Fusion Compiler-Custom Compiler-PrimeTime STA) flow.

Senior Member of Technical Staff, SOC Design, Intel Corp, CA [March 2011 – Nov 2019]

•Owned the implementation of two ASIC sub-system blocks in the latest generation 10nm node. This included MV (multi-voltage) design architecture, UPF-based low-power hierarchical synthesis using DCT/DC-NXT, Floorplanning/PnR in ICC2, Formal Verification at block and sub-system level using Conformal, power computation and RV analysis using PTPX and Apache.

•Worked with multiple IP teams cross-functionally and defined top-down design requirements. This included logical to physical partitioning from ASIC top-level to sub-system, IP and block-level. Provided guidelines in doing design trade-offs between low-power, high-speed, area & reliability.

•Previously managed the tapeout of production 14nm SOC with 100+ M instances. This included RTL/netlist top-level integration, floorplanning, timing closure, UPF low-power, LEC and full-chip signoff. This also included managing different IP teams, making sure that they delivered IP collateral on time and with compliance to the defined metrics.

•Earlier responsibilities included timing signoff of a 20nm SOC. The full-chip STA included working with multiple IP owners, overseeing timing budgets for every IP block, timing model generation, routing interface and netlist generation of custom configurable blocks for PT-STA.

•Managed the tapeout of six different (40nm) ASICs in Hard Copy Design Center, whereas two of them ended up being used in the Orion spaceship. These designs ranged from 10M to 20M instances with a throughput of 6.5Gbps. The last design resulted in generating revenues of $30M over a period of 5 years.

•Some of my earlier front-end work included reviewing customer netlist, re-architecting PLLs’ clocking structure, recommending sdc changes for IO interfaces like DDR, CDC and SERDES etc., ensuring the right AIOT (Advanced IO Timing) model usage and IBIS-based board simulations, verifying critical FPGA and HC ASIC timing waveforms in Quartus and PrimeTime, EPE (Early Power Estimation) and final power computation including ODC (On-Die Capacitance).

•My backend tasks included overlooking the whole flow for tapeout. This included DC synthesis, ICC P&R, Star-RC extraction and PTSI-STA, followed by ECO cycles, double-via, metal-fill, DRC/LVS, and RV.

•In parallel, I conducted weekly tag-up with the customers where I updated them of our current status in the project schedule. Based on our progress/glitches, I provided forward estimates for remaining stages of the flow and updated the project schedules accordingly.

Senior Staff Corporate Applications Engineer, Synopsys Inc., CA [April 2006 – Mar 2011]

•Managed the tapeout of multiple ASIC designs at 90, 65, 45, 32 and 28 nm nodes. The design sizes varied from 500K to 60 million instances.

•Some of the engagement accounts I worked with include Intel (Beckton), ST (Grenoble), Broadcom (San Jose), QualCom (San Diego) and Toshiba (NSKK, Japan).

•Led the proliferation of “IC Compiler Recommended Methodology (ICC-RM) to ASIC customers.

•Previously responsible for the success of ICC Milkyway-based flow, Verilog + DEF flow and the complete ECO flow.

•Earlier contributed towards the success of MCMM (Multi-Corner Multi-Mode) Flow in ICC.

•Developed and delivered multiple WebEx presentations including ICC MCMM training and methodology on handling PG /tie nets to Application Consultants and customers worldwide.

•Designed and developed ways to enhance the ECO engine for MV/UPF flow.

•Actively worked in a cross-functional manner across multiple R&D/CAE teams to get closure on the ARM 9.0 design issues. This included my work as a liaison between the MW, data model, UPF and Formality teams.

Senior Member of Consulting Staff, Cadence Design Systems, CA [June 2003 – Feb 2006]

•Managed multiple accounts at a time including Agere, Philips and ST and worked with Marketing to work through PRS (Product Requirement Specification) documents acceptable to both R&D and Marketing.

•Led the TurboEagle Design from RTL to GDSII: This included a DSP core, DES, USB and a lot of RAM and ROM macros. Implemented the first rev in 0.18u, second in 0.13u and the last in 90nm technology. The entire design was implemented using Cadence RTL Compiler for Synthesis, SOC-Encounter for CTS, Place & Route and Physical Optimization, Qx for

RC-Extraction and CTE (Common Timing Engine) for STA.

•Developed a hierarchical flow for ASIC Signoff. The Block-Implementation includes steps as Preplace-STA, Load-FP, Detailed-Place, PreCTS-Opt, CTS, Pwr-Analysis, PostCTS-Opt, Route, Verify, SI_Analysis, PostRoute-Opt, SI_Repair, Mfg-Opt, Signoff-SI, Signoff-Power,

Generate-Block-Models, Generate-GDS, and Create-Final-Data steps.

•Worked on a low-power MSMV (Mixed-Signal Mixed-Voltage) Design: The design was implemented using multi-threshold libraries, level-shifters, isolation cells and power switch array across multiple power domains.

Principal Engineer, Canesta Inc, CA [Dec 2001 – June 2003]

•Headed a team of engineers designing a mixed-signal system for a virtual keyboard module which includes a sensor array chip, optical lens and filters, image projection and microprocessor-based memory subsystem ASIC.

•Managed various ASIC projects and worked with customers & OEMs/ODMs to identify needs and translate them into product requirements, and worked across Business Development, Marketing and Design Teams in finalizing the MRDs (Marketing Requirement Documents) for productization.

•Architected the design methodology as follows: Logic Synthesis and scan-insertion using Build-Gates, ATPG using Syntest, Place & Route and scan-reorder using Apollo and PKS, and detailed timing analysis of Multi-Cycle Paths (MCP) using FE-STA.

•Allocated necessary resources as follows: Design of the embedded system core using

V-Automation 80186 microcontroller IP and USB IP, RAM/ROM models and I/Os from Dolphin and std-cells from Artisan.

•Assigned responsibilities to design and verification teams for their individual tasks as follows:

•Logic Synthesis of the microcontroller and USB IP RTL

•DFT of the above, which also includes on-chip RAM and ROM MemBIST.

•Verification of the microcontroller-memory interface using Denali.

•Outsourced P&R to third-party (TTM) and worked closely to ensure a successful tapeout.

•Successfully delivered projects on time with effective work planning: This included forward estimates of remaining schedules to be completed and projected schedules of milestones to be met. Maintained project plans in biweekly reports.

•Worked with Canesta Sales Channel to close a $5 million toolkit OEM agreement with Samsung.

•Successfully worked through a Risk-Management plan which saved the company from dire straits at one point in time.

EDUCATION

MS in Electrical Engineering

California State University, Northridge, CA

BS in Electrical Engineering

N.E.D. Engineering University

TECHNICAL SKILLS

Logic Verilog-XL, VHDL-XL (Cadence), ModelSim (MTI/Mentor) Simulation: VCS (Synopsys), ViewSim, ViewTrace (ViewLogic)

Logic Design Compiler, DC-Topo, DC-NXT, Fusion Compiler,

Synthesis: Synplify (Synopsys)

BuildGates (Ambit/Cadence), RTL Compiler (Get2Chip/Cadence) VHDL-Designer, VSM, ViewGen (ViewLogic)

ATPG: Tessent, DFT Advisor, Fast Scan (Mentor Graphics),

TurboScan (SynTest Technologies)

Tetramax, Test Compiler (Synopsys), Verifault-XL, Encounter-Test (Cadence)

Floorplanning/ IC-Compiler/ICC2, Jupiter-XT, Astro-PC, MilkyWay, Apollo

(Synopsys/Avant)

Place & Route: Innovus, First Encounter, AmoebaPlace, PlaceDesign, wRoute, NanoRoute (Cadence), LSI-FlexStream, LSI-Toolkit (LSI Logic)

Power: Power Compiler, PT-PX/PrimePower (SNPS),

SOC-E, VoltageStorm (Cadence),

Reliability: RedHawk/Totem (Apache)

RC-Extraction: Star-RCXT (Synopsys), FEX Native Extractor (Cadence), QX/Fire & Ice (Simplex/Cadence)

SI/ PT-SI (Synopsys), CeltIC (Cadence)

STA: PrimeTime (Synopsys), Tempus, FE-STA, FE-CTE (Cadence),

Formal Conformal Verification: Formality

Functional SystemVerilog

Verification: UVM/OVM

Debug: MIPI, GDB, System Console (Intel), Eclipse

FPGA Foundry: Xilinx Design Manager, XACT Development System (Xilinx) Altera Quartus & Integrated Design Environment for FPGAs (Altera/Intel), QuickLogic's SPDE Tools (QuickLogic)

Gate-Array Stratix, Cyclone & HC series (Altera), Virtex, Spartan, and XC series: (Xilinx)

Devices: QL-Class Devices (QuickLogic), ATT 's ORCA family of devices (Lucent) Schematic CMDE Schematic Editor (LSI Logic), ViewDraw (ViewLogic),

Capture: Capture XDE (Xilinx), ORCAD's Draft (Orcad), Design Vision (Synopsys)

Bus Protocols: PCIe Gen1-Gen4, USB, SPI, I2C, AXI/APB, MDIO (UART), AGP, Fire-wire

Memory Interfaces: DDR, HBM & NVME SSD

DSP Blocks: IEEE Double-Precision (DP) 53x53 signed-magnitude (SM), SP 24x24 SM. INT 64x64, 32x32, 24x24, 16x16 and 8x8 signed/unsigned multipliers, IEEE 754 FP SP18, high-precision (27 bit) multiplier, interpolator and decimator blocks.

Languages: Verilog, VHDL, TCL, Python, Perl, C, Fortran, Basic, Assemblers for ARM, 6502 & Z-80.

Project MS-Project, MS-Excel,

Management: SmartDraw, SharePoint

Technical Publications

•Flat Implementation Hierarchical Methodology (FIHM) – a novel way to generate IP timing models (IPPTC 2017 Intel Best Paper Award).

•Challenges in Implementing a First-Ever 14nm Test Chip at Altera (ATS2014)

•MCMM Optimization Methodology – The Indispensable Approach to ASIC Design (ATS2012)

•Process variations and DFM (Altera 2012)

•Debugging a Verilog + DEF Flow

•Recommended ECO Flow Usage for IC Compiler ...

•How to Run Freeze-Silicon ECO in IC Compiler …

•ECO Flow Application Note Rev. 2

•Signal Integrity Effect on Generating Coupling Capacitances

•Coupling Capacitance Filtering in the Multicorner-Multimode Flow

•Avoiding Mismatch in Instance Names Between the gate-level VHDL and SDF...

•Verifying Analog PG Nets in Non-UPF Mixed-Signal Designs.

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