Design Engineer Controller

Elbert Shiang

Palo Alto, CA ************@*****.*** 408-***-****

SUMMARY

Accomplished 6 ASICs and 10 FPGAs from functional specification to the final production.

Experienced in Digital and Mixed-Signal SOC design including chip architecture, RTL implementation, RTL synthesis, ASIC bring-up, and characterization.

Experienced in Firmware development.

Led multiple large-scale projects from specification to final production in the area of chip, board and firmware designs.

SKILLS

FPGA/ASIC Tools: Xilinx, Altera, Cadence, and Synopsys.

DSP: wireless microwave, power control.

Wireless: QAM and BPSK.

Interface Protocols: Ethernet, TCP/IP, SONET, Flash Controllers, SATA, SAS, FC, FCoE, PCIe, USB, SMB, I2C, SPI, SDIO, NCSI, DDR2/DDR3/DDR4, and SRAM.

Programming Languages: Verilog, UVM, VHDL, C/C++, x86 Assembly, MATLAB, Perl, and Python.

Video Codec: H264, VGA, and HDMI.

Encryption: AES.

Operating System: Linux and Microsoft Windows.

Lab equipment: Oscilloscope, Logic Analyzer, Network Analyzer, and Spectrum Analyzer.

Machine Learning: Online class in Stanford.

3D system/video processing: Golf emulation system using high speed dual cameras.

CPU integration: ARM CORTEX-M4 MCU, ARM Cortex R4, MIPs.

SDK Tool: Keil, Eclipse.

PROFESSIONAL EXPERIENCES

(Encore Semi Inc) Wave Computing, Inc. 2018, December – present

Principal Engineer

Developed and debugged DDR4 in the AI ASIC.

oDebugging and bring-up the DDR4.

oCreated the model of transmission line and preformed the signal integrity analysis.

Developed and debugged the MIPs muticore FPGA AI system using HAPS80 and MIPS.

oReview the schematic and debug both I/O and south bridge card.

oConfigure the system including clock, reset, I/O voltage, port/trace mapping for HTS bus, configure PCF, TSS constraints.

oPartition the design into 4 FPGA( XilinxUV440) and debug the system for HAPS80 using Protocompiler and Xilinx Vivado.

oDesign the flash write and read program for U_boot using TCL.

oBring-up and debug the Linux 4.14 system.

(Encore Semi Inc) Micron Technology, Inc. 2017, May – 2018, December

Principal Engineer

Developed and debugged SSD LDPC Encoder/Decoder firmware model using Eclipse/GCC/C for SSD controller.

osource code of management of system tags, reference Queue, metadata, memory, CRC, parity, command queue, status queue and thread.

ohardware abstraction layer and register.

ocreate the block diagram and documentation for Decoder/Encoder model based on (data/metadata/CRC/LDPC).

Developed and debugged FPGA HAPS80 emulation.

oFPGA remote control script using Python.

odebugged FPGA/Firmware using MDB from Synopsys.

Developed and debugged SSD LDPC DECODER and ENCOREDER firmware model using Eclipse/GCC/C.

Developed and debugged CPU firmware model.

Developed and debugged Block Memory API(BMG) model.

Experienced tools: Use Jenkins for system automation control. Use git/medal for repository control, Use ETX (Exceed TurboX), LDAP (remote directory access) and NIX (cross platform management) as remote access software solution for Linux and Windows. Use Jira for bug tracking, issue tracking, and project management.

Cytek Biosciences Inc. 2016, Nov – 2017, May

Consultant

Developed and debugged cytometry system both FPGA Xilinx Artix-7 XC7A100T using 50M Hz clock for function including decimation and low pass filtering for 8 channels each having16-bit 80M Hz ADC out of analog signals amplified from laser detection signals sensed from scattered and fluorescent light after laser light passing through sheath flow mixed with blood flow and FPGA Xilinx XC6SLX9 for arbitrating and managing different I/O requests using 50M clock and 48M USB clock for flow cytometry system including software subsystem, Excitation subsystem, Fluidics subsystem and electronic subsystem with 6 PCIe bus line cards offering 64 acquisition channels.

Amp’ed RF Technology 2015, August – 2016, March

Consultant

Developed FPGA emulation and ASIC system including chip top integration, ram/rom/PLL generation, pin assignment using the Cyclone 5 E development KIT with Altera Cyclone V 5CEFA7F3117N FPGA for IOT module with ARM CORTEX-M4 MCU, ROM, SRAM, UART and SPI interface running at 200MHz.

Developed and debug the Embedded firmware written in C for the boot ROM using ST SDK and generating the ROM hex file from the bin file generated from Keil compiler.

Developed the device driver of SPI(interface to Wi-Fi & BLE &flash module) and UART for ARM CORTEX-M4 MCU.

Multibeam, Corp. 2014, December -2015, July

Consultant

Implemented BSE (backscattered electrons detector) for the CEBL (Complementary E-Beam Lithography) through PCIe Gen2/Gen3 interface with FPGA system controlling the DAC Electronic beam scanner and ADC Electronic beam detector using Xilinx XC6VLX240T chip running at 250 M Hz.

Intel, Inc. 2014,July – 2014,October

Consultant (3 months)

Implemented and compiled the firmware using C which configured the UART port to initialize IO, the video and audio as well as dump the memory content from internal bus to Putty emulator by using Nanocore toolchain.

Compiled and generated the FPGA image of Altera FPGA (EP4SGX230C2) for the Indian Hill (IHL) which is a low power wearable device interfaces with the end user touch-free, command voice recognition, gesture/pose recognition and predefined face or scene recognition using Quartus II and software tools.

Samsung, Inc. 2013,September-2014,February

Consultant (6 months)

Integrated DDR3/DDR4 IP into the Cortex M3 and Cortex A57 with RTL simulation and emulation. The emulation system based on Synopsys HAPS6 uses Xilinx VC6VLX760FF1760 running at 10MHz.

Device driver for init DDR4.

Brought up the DDR3 UDIMM emulation system through defining the I/O pad, pin assignment, synthesis using simplify, debugging using ChipScope, Certify, and Oscilloscope.

Enphase Energy, Inc. 2011-2013

Senior ASIC Design Engineer

Led the design and development of FPGA emulation system for the 250W Inverter using Xilinx S6LX150T; and subsequently ported the design onto a 65-nm ASIC.

Implemented advanced DSP algorithms for the next generation cycle micro-inverter technique: voltage normalizer, state space observer controller, DC offset compensator, delay compensator, radius calculator, trajectory controller, and fault detection controller.

Integrated 3rd party AES IP and collaborated with SW team on the architecture of encryption usage models in the inverter ASIC.

Architected and designed ADC characterization system for a 1 MHz ADC.

EDUCATION

M.S. in Electrical & Computer Engineering University of Arizona, Tucson, Arizona.

B.S. in Electrical Engineering National Taiwan Ocean University, Keelung, Taiwan.

PATENT

Chattopadhya, S.; Kruk-Chattopadhya, M.; Sandhu, H.; Shiang, E.; Raza, A. 2009. Method and Apparatus for Enabling Voice Communication. U.S. Patent Application 200********. Filed August 2009. Patent Pending.

Full ECL compatible GaAs digital circuits with temperature compensation.

PUBLICATION

“APTMC: An Interface Program for use with ANSYS for Thermal and Thermally Induced Stress Modeling and Simulation of VLSI Packaging”1987 ANSYS Conference Proceeding, 11.55-11.62.

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