Computer Engineer

Josue Chavarria **************@*******.*** 408-***-****

www.Linkedin.com/in/JosueChavarria

TECHNICAL SKILLS & COURSE WORK

● C, C++, Python, Javascript, Verilog, System Verilog(beginner), Perl(beginner), TCL(beginner)

● Data Structures & Algorithms, Object-Oriented Programming

● FPGA Design, MIPS Assembly Language, Computer Architecture

● Real-Time Embedded Systems (FreeRTOS), Serial Communication Protocols (SPI, UART, I2C)

● Compiler Design, Microprocessor Design, Oscilloscope, Multi-Meter, Logic Analyser, Function Generator

● Information Security, Cryptocurrency & Blockchain, Database Systems (SQL), Network Protocols, Soldering EXPERIENCE

OTA Associate Engineer - Element Materials Technology April 2022- April 2023

● Performed LTE/NR TIS, TRP, and A-GPS testing on client samples to meet cellular provider requirements

● Troubleshooted and resolved sample connection and testing equipment issues

● Verified and reviewed test setup, configuration, and results for accuracy to maintain high testing quality

● Performed chamber maintenance through goldens and range loss testing

● Contributed to the development of Antenna Measurement Software EmQuest Executive PROJECTS

MIPS Processor - CMPE 140: Computer Architecture and Design Spring 2021

● Designed a 32-bit 5 stage pipelined MIPS processor on a Xilinx Basys 3 Artix-7 FPGA Board with Verilog

● Completed FPGA implementation with an SoC integrating the processor with a factorial accelerator and GPIO unit

● Performed functional verification and hardware validation using test benches and simulations MP3 Player - CMPE 146: Real-Time Embedded Systems Spring 2021

● Developed an MP3 Player using NXP’s LPC408/407x microcontroller in C

● Implemented with FreeRTOS using tasks, queues, binary semaphores, and interrupts

● Reviewed datasheets, user manuals, and documents to implement drivers for hardware peripherals

● VS1053 MP3 Audio Decoder (SPI), LCD Screen (UART), Buttons (GPIO Interrupts), Joystick (ADC) Microcomputer - CMPE 127: Microprocessor Design Spring 2020

● Designed and built a microcomputer, complete with a microprocessor unit, address bus, address decoding circuit, control bus, data bus, SRAM, I/O interface, interrupt structure, and keypad as an input device

● Integrated Circuits used: Bi-directional Bus Transceiver, Octal D-Type Transparent Latches, 3 to 8 Line Decoder, SRAM 16K, Programmable Peripheral Interface System Level Design Integer Division Module - CMPE 125: Digital Design II Spring 2020

● Designed the microarchitecture for an integer division algorithm in Verilog

● Designed an ASM chart, microstructure diagram, and state transition diagram for the system

● Implemented system with a CU that gave signals to a DPU and received status signals

● Wrote test benches and ran simulations for functional verification and used an FPGA board for hardware validation

EDUCATION

B.S. Computer Engineering San Jose State University GPA 3.43 Graduation: Spring 2021

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