| Resume alert | Resumes 41 - 50 of 104 |
Design Project
Placentia, CA, 92870
... Ram Meghe Institute of Technology & Research, Badnera, INDIA August 2010 – June 2014 Bachelor of Engineering in Electronics & Telecommunication, GPA: 3.48 Knowledge Areas Digital Systems design with FPGA CMOS VLSI Design Low Power Digital IC Design ... - 2017 Jun 24
... Ram Meghe Institute of Technology & Research, Badnera, INDIA August 2010 – June 2014 Bachelor of Engineering in Electronics & Telecommunication, GPA: 3.48 Knowledge Areas Digital Systems design with FPGA CMOS VLSI Design Low Power Digital IC Design ... - 2017 Jun 24
Engineer Design
Fullerton, CA
NITIN MISTRY 714-***-**** aczjeb@r.postjobfree.com OBJECTIVE To obtain a challenging permanent position as an FPGA Design Engineer where my experience and educational training will provide valuable contributions to a company’s objectives. Summary Of ... - 2017 Mar 28
NITIN MISTRY 714-***-**** aczjeb@r.postjobfree.com OBJECTIVE To obtain a challenging permanent position as an FPGA Design Engineer where my experience and educational training will provide valuable contributions to a company’s objectives. Summary Of ... - 2017 Mar 28
FPGA / ASIC Design Engineer
Fullerton, CA
Stephen Cole **** ********** ***, *********, ** *2835 Email: aczhiq@r.postjobfree.com Relevant Qualifications: ASIC / FPGA Design Engineer with over 15 years’ experience of design, implementation, simulation and co-verification of Verilog and VHDL ... - 2017 Mar 25
Stephen Cole **** ********** ***, *********, ** *2835 Email: aczhiq@r.postjobfree.com Relevant Qualifications: ASIC / FPGA Design Engineer with over 15 years’ experience of design, implementation, simulation and co-verification of Verilog and VHDL ... - 2017 Mar 25
Matlab, PSpice, hardware, circuit design, gate level logic design
Long Beach, CA
... PSpice, NI Multisim, Agilent Advanced Design Systems (ADS), Altium Designer Assembly Languages: 8085, 8086, 8051 Hardware: FPGA-Spartan 3E, Spartan 6, Nexys 4, Artix-7, Altera Quartus II Test and Measurement Equipments: Spectrum Analyzer, Network ... - 2017 Feb 11
... PSpice, NI Multisim, Agilent Advanced Design Systems (ADS), Altium Designer Assembly Languages: 8085, 8086, 8051 Hardware: FPGA-Spartan 3E, Spartan 6, Nexys 4, Artix-7, Altera Quartus II Test and Measurement Equipments: Spectrum Analyzer, Network ... - 2017 Feb 11
Electrical Engineer Design & Test
Irvine, CA
... Experience: Strong technical leaderships in Electrical Engineering where I can design Altera FPGA, evaluate, and validate Hardware/Software, RF, WiFi, AC/DC Power, reliability, Root-Cause Analysis, Statistic Analysis, Six Sigma, Project Management ... - 2017 Feb 01
... Experience: Strong technical leaderships in Electrical Engineering where I can design Altera FPGA, evaluate, and validate Hardware/Software, RF, WiFi, AC/DC Power, reliability, Root-Cause Analysis, Statistic Analysis, Six Sigma, Project Management ... - 2017 Feb 01
Project Design
Tustin, CA
... Synthesizers: Synopsys Design Compiler, RTL Complier, FPGA Express, Leonardo Spectrum, Xilinx Tools, Synplicity. Operating Systems: Windows 95/98/NT/2000/XP, Vista, Window7, UNIX, LINUX. CMOS Technology: 90nm,65nm, 45nm, 32nm, 20nm, 14nmFINFET. ... - 2016 Nov 30
... Synthesizers: Synopsys Design Compiler, RTL Complier, FPGA Express, Leonardo Spectrum, Xilinx Tools, Synplicity. Operating Systems: Windows 95/98/NT/2000/XP, Vista, Window7, UNIX, LINUX. CMOS Technology: 90nm,65nm, 45nm, 32nm, 20nm, 14nmFINFET. ... - 2016 Nov 30
Electrical Engineer Engineering
Rancho Santa Margarita, CA, 92688
... 2014 – May 2016 Created and maintained software test suite for hardware components using Visual Basic and TCL Worked with Xilinx FPGA tools (Vivado) to implement digital audio receiver/transmitter with Verilog Utilized hardware diagnostic tools to ... - 2016 Aug 29
... 2014 – May 2016 Created and maintained software test suite for hardware components using Visual Basic and TCL Worked with Xilinx FPGA tools (Vivado) to implement digital audio receiver/transmitter with Verilog Utilized hardware diagnostic tools to ... - 2016 Aug 29
Engineer Computer Science
Irvine, CA
... Internship Experience FPGA Intern, Ixia, Calabasas CA 5/2012-8/2012 • Developed the architecture and programmed a five layer parsing checksum engine in VHDL. • Designed architecture for future work in a timestamp engine. • Created a self checking ... - 2016 Jul 12
... Internship Experience FPGA Intern, Ixia, Calabasas CA 5/2012-8/2012 • Developed the architecture and programmed a five layer parsing checksum engine in VHDL. • Designed architecture for future work in a timestamp engine. • Created a self checking ... - 2016 Jul 12
MD-ENG-j4
Irvine, CA, 92602
... various processor specific and customer specific bus structures ● Experience designing complex digital systems using CPLD and FPGA devices (XILINX and ALTERA) ● Experience with System-On-Chip (SOC) development ● Experience with DOD Anti-Tamper (AT) ... - 2016 Jul 11
... various processor specific and customer specific bus structures ● Experience designing complex digital systems using CPLD and FPGA devices (XILINX and ALTERA) ● Experience with System-On-Chip (SOC) development ● Experience with DOD Anti-Tamper (AT) ... - 2016 Jul 11
Engineer Quality
Westminster, CA
... Produced test procedures for Programming Controller cards, test diagrams using Xlinix iMPACT for FPGA/CPLD devices. Designed board level test fixtures for production and repair depot. Using DMM and oscilloscope to troubleshoot systems down to ... - 2016 Jun 13
... Produced test procedures for Programming Controller cards, test diagrams using Xlinix iMPACT for FPGA/CPLD devices. Designed board level test fixtures for production and repair depot. Using DMM and oscilloscope to troubleshoot systems down to ... - 2016 Jun 13