Nikhil A Kothari

Summary of Skill Sets

oAnalog Mixed Signal, Design Analog Circuits to low power, ASIC interface applications

oLayout Verification, Floor planning, Module level design & Multi-Chip-Module layout/development/Cache Memory design.

oTop Level Simulation Test & Debug, Verilog (4 years), C programming (4 years) and RTL

oFPGA (4 years), ARM 7, 8, 9 and 10.

Technical Skills

Programming: VHDL / Verilog HDL, PERL, System C, Vera, C, C++, keil C, Fortran, Assembly language.

Simulators: Xilinx ISE, Vivado Suite, LabVIEW, Matlab, NC Verilog, Verilog XL, ModelSim, AMS.

Synthesizers: Synopsys Design Compiler, RTL Complier, FPGA Express, Leonardo Spectrum, Xilinx Tools, Synplicity.

Operating Systems: Windows 95/98/NT/2000/XP, Vista, Window7, UNIX, LINUX.

CMOS Technology: 90nm,65nm, 45nm, 32nm, 20nm, 14nmFINFET.

Electrical & Controls: SCADA Architecture Planning and Designing, MS Office2012 Package, XML, Digital design,

Industrial Automation: Siemens, Schneider PLC programming, HMI, delta plc, Honeywell PLC, EPlan.

Electronics Design: Microwind for VLSI CMOS design, Microcontroller design, OVM, UVM, RTL, Design development

Verification, digital design verification, analogue design verification, SVA,

Fundamental knowledge of Operation of High Speed of SERDES IO.

Research: VOIP for Quality of Service in wired and wireless medium for Cloud Computing.

This research was carried out under guidance of Dr. Charles Liu who is working with NASA into networking field.

-Factors effecting the Quality of Service.

-Bandwidth utilization in VOIP for wired and Wireless.

-Load balancing of traffic and improvement of the quality of Service.

-Measuring MOS in various test conditions.

Various test case was simulated for different cases to analysis the quality of service by implementing various encoding.

Cache Design Project

Designed 16-bit memory byte addressable.

- Designed cache size of 64 bytes each and block size is 1 word.

- Designed Direct Mapped Cache(DM).

- Designed Fully Associative Cache (FA) and Two-way Set associative (2-Way) cache using LRU replacement policy.

- Analysis studied by varying block size 1-word block, 2-word block and 4-word block for Direct Mapped cache, Fully Associative Cache and 2-way set associative cache.

- Analysis studied by varying Cache size 64 bytes, 128 bytes and 256 bytes for Direct Mapped cache, Fully Associative Cache and 2-way set associative cache.

- Explored the effect of set associativity for 64-byte cache and 1-word block impact on:

- 1-way set associativity (same as direct mapped cache in part 1).

- 2-way set associativity (same as 2-way set associative cache in part 1).

- 4-way set associativity

- 8-way set associativity

- 16-way set associativity (same as fully associative cache in part 1).

Testing of the cache was done with benchmark file by developing test inputs to verify the design.

Professional experiences:

Sr. Electronics Engineer, Einfochips Pvt Ltd. Jan 2013- Oct 2014.

-Worked on multiple project assignments for different clients in various technological nodes

-Worked as a Mask Design Engineer in the full duplex Intel LVDS I/O in FinFET 14nm.

-RTL design verification was successfully implemented.

-Implemented and improvised a Proof-Of-Concept Layout Design for Video DAC called the VID DAC using the 180nm power BCD PDK library with area constraint of 195μm x 245μm.

-Utilized Wallace tree algorithm to design multiplier to meet high speed DSP requirements.

-Improved data path timing at RTL level, and used Apollo for timing-driven placement and routing at layout level.

-Designed basic gate cells and I/O pads at transistor level, and conducted rigorous verification.

-Utilized PLLs to generate on-chip high-speed clock frequency.

-Completed all custom design flow, including DRC and LVS using Avant! Tool suite.

-Parameter extracted from back annotated simulation for physical verification.

-Designed general purpose DSP chip, and 16-bit fixed-point RISC CPU chip.

-Programming done on assembly language and scripting tools used as shell scripting for Linux.

-Vital member of research group involved in HDL simulation and HDL RTL architecture coding.

-Behavioural RTL debugging was carried out in the project.

-Designed RF/Analog Layout of stand-alone LNA (Low Noise Amplifier) and PA (Power Amplifier) chips in TSMC RF 45nm Process.

-Digital layout Design of 16-bit pipelined ADC in TSMC 250nm technology

-Successfully completed block timing closure.

-Digital Layout Design of Full Custom 256x4 SRAM using TSMC 160nm to achieve minimum power and area

-LVDS Layout Design and Enhancement in TSMC 20nm technology

-Digital Layout development of 16 track high speed Standard Cell Library in TSMC 90nm/65nm

-Design and Characterization of CMOS Digital Circuits, 6T Bit Cell of SRAM, I/O Circuit

-Design, simulate, debug and test Xilinx FPGAs for low power, miniature spectrometers.

Project Name: DAC

-Product architecture development and simulation which includes system trade off and architecture selection, justification, power planning was done

-Top level simulation, Test, measurement and debug of IC design using standard RFIC lab equipment’s.

-Implemented Differential Amplifier using CMOS35 Nano microns with step-wise Fabrication Process.

-RTL verification was critical in this projects due to several constrains in design.

-DRC and ERC check rules for design and electrical were successfully implemented and verified.

-Performed P&R from Netlist to GDS including timing closure

-Physical verification was successful conducted for this design in duration of three months’ time.

-SAT based debugging was performed

-ABMA 2 protocol was successfully implemented

-VHDL coding for hardware and test bench implemented successfully.

Project Name: Conversation of waveform

-Implemented by Schmitt Tigger circuit for conversation of sinusoidal wave to Square wave on CMOS 25 Nano microns.

-Module level design & Multi-Chip-Module layout, development.

-Working within a team of highly committed individuals to execute high performance IC designs in a demanding & time sensitive environment

-RTL and HDL coding successfully implemented.

-Test, measurement, and debug of your IC designs using standard RFIC lab equipment’s.

Project Name: MIPS CPU Processor Design Project 32 Bit.

-Worked on developing initial design concept to floor planning and verification process

-Performed analysis of design layout as per client requirement defining location of predefine cells in design phase.

-Optimization of Place and Route with timing closure was performed by keeping setup and hold constrains as per design requirements of the client.

-Implemented Signal Integrityusing entasys design tools which help to minimised and fix the Si problem in chips.

-Performed power planning by taking care of IR drop of static and dynamic.

-Successfully handled block and top level complexity from floor Planning during P&R Verification process.

-Managed tasks of integrating physical database and performed debugging of physical design implementation

-Provided software support and in power domain verification flows.

-ExecutedDFT and analysis of static timings

-Developed a Modified MIPS Processor using Xilinx ISE and coding in Verilog language.

-AMBA 3 protocol was successfully implemented.

-Work involved Functional Verification of blocks in IP and SOC, tracking of the requests and the responses based on priority between the layers and the blocks, Functional Coverage, Code Coverage, Designing and Integrating of Test Bench Components, Developing Test cases, Assertions, Sequences, Debugging, Regression analysis.

-Clocked assertion was implemented in this project.

-Verification of IO and Logical blocks in an IP

-SAT based and RTL based debugging was implemented.

-Debugging, coverage and regression analysis verification of Memory block in a SOC

-RTL debugging for ip block and designed sequences and test cases using Verilog.

Project Name: SCR_v, Phyhy_revd

MBIST, Failure Analysis, VCS Simulations and Scan Insertion.

-Snapdragon MSM8x26 – 28nm with 1.4 Ghz A6 Cortex.

-Snapdragon Msm8926 – 28nmwith 1.8 Ghz A6 Cortex.

Project Name: Analog IC design for Israel client

-Designed analog circuits for low power, low cost capacitive and resistive sensing ASICs.

-Designed low power oscillators and interfaced with layout contractor for post layout verification.

-Layout of mixed signal blocks, Parasitic Extraction, RC Timing check, Routing, Guard rings, Floor Planning.

-Analog-Mixed signal verification at chip level.

-Managed Analog Mixed-signal CMOS design team of 4 IC designers that developed and released all current Synaptic’ low-power, low-cost capacitive sensing ASICs for human interface applications (e.g., Touchpad and Touchscreens).

Project Name: ASIC Cache Coherency

-Verified 400,000 gate block in a multi-million gate cache coherency ASIC for an IA-32 based multi-processor system using Spec Man Elite, Verilog, and VHDL to ensure 1st silicon success.

- Developed solutions to test inter-partition messaging – bringing new functionality.

- Created methodology to carry verification techniques into laboratory which saves time by eliminating repeated

testing

Sr. Electrical Engineer, Amee Power Drives, April 2009 – Dec 2012.

-Developed SCADA Architecture for collecting data from various sensors of the mall.

-Worked as a BMS Project Engineer + Energy Management system at site for Mangalore City Center Mall. Designed, Implemented and tested complete system which was commissioned within the time frame.

-Coordinated with Client & L&T on site at Mangalore with various vendors of BMS.

-Evolution of work from ground people & providing them solution to carry out work in easy & efficient way to manage the dead line of the Project Commissioning.

-Power electronics design and development for various projects include IGBT, MOSFET, LOW POWER, LOW NOISE design.

-Co-coordinating with various vendors for finding suitable solution of problem to complete the project.

-Programming of BMS executed successfully which is embedded system part of the project. L& T Hizzra & Ahmednagar Awarded with Golden & Silver Rating by Godreg & Beyoncé.

-Researching, designing, testing the device which are manufactured.

-Monitoring the engineering life cycle of devices to execute them correctly.

-JTAG programming for microcontroller and ASIC chips.

-Customized embedded designs for Automation Control Systems.

-Energy meter programming using Infrared for L&T.

-Wireless Robotic arm for lifting heavy objects for Company.

-Fortran used for graphics design and development for developing UI for customized client.

Project: Integration of CAN VIP into existing Mixed Signal IC test bench:

-Responsible for the integration and modifications of CAN VIP corresponds to changing RTL for given IC specifications.

-Testing of CAN on FPGA board: Tested CAN on Altera using Quartus II.

-Modifications in existing test bench for FPGA simulation which included multi-chip simulation.

Project: Designing of Analog PLL and Layout designing.

-I have successfully Designed all the blocks of a PLL along with an Automatic gain control circuit in 1 μm CMOS Technology and integrated them for testing the PLL circuit. The fundamental frequency of the PLL is 30MHz and the VCO can vary between 28.5MHz and 31MHz frequencies for 1v variation in the control voltage. The PLL mentioned is made immune to the variations of the input signal amplitude between 500mv to 1100mv with the help of an Automatic gain control system. The total number of MOSFETs in this Design are 106. Layout design is carried out for VCO and Phase detector. Entire Project is done in Tanner tools version 7.10.

Project: Principal project leader for SCADA, January 2011- Dec 2012.

-Worked directly with new and existing clients to develop new projects. Developedproject scopes of work and negotiated fees for new projects. Prepared bids and proposals for presentation to clients for new work.

-Managed project budget, schedules and quality of deliverables. Responsible to company share-holders for profit and loss of projects.

-Development of POWER Control board which handle DC to DC power requirement.

-Managed shared resources and personnel, coordinating with project managers of different projects in order to meet project budget and scheduling requirements.

-Responsible for work assignments and daily activities of employees including administrative, engineers, technicians and tradesmen.

-Managed in-house customized panel fabrication as per client. Responsible for development and submittal of fabrication drawings, procurement of materials and scheduling of panel fabrication.

-Coordinated factory testing with end users/clients.

-DVT testing successfully completed for the project and green certification was provided by GODREJ and BEYONCE.

-Developed designs and PLC/HMI programs for SCADA systems, distributed plant control systems and standalone processes and facilities.

-Maintained technical responsibilities for various PLC/HMI programming and Instrumentation and Control design projects.

-Implemented Energy Management system to collected reading from each and every energy meter to calculate cost of electricity and for billing purpose.

Matlab Projects

Analysis of Various Filters used in Control signals for Frequency Monitoring.

-The project was related to analysis of control signal frequency response using combination of various filters with various frequencies starting from Min 1 KHz to Max. 1 GHz.

-Low Power analogue system design and verification

Analysis of Crypto techniques used for encoding and decoding.

-The project undertaken to study the various cryptography encryption process using Hill Cipher for Money transfer Messages and calculating the time delay and efficiency of the Math code and checking the Differential Attack probability.

-Analysis of DOS and DDOS attack were studied by model and then implemented.

LabVIEW Projects

Developed two applications to implement a real-time monitoring and control software system which predict the lifetime of Active Heaters: Implemented real-time embedded software to set up system parameters and monitor various heater parameters used to predict heater life.

Project: Wafer Processing

-Developed architecture and design for software to control and monitor a 200 mm wafer processing system.

Artificial Intelligence.

-Self-Learning of AI using GAOT (Genetic Algorithm Optimization Toolbox) for supporting genetic Tree and Understanding the complex architecture of Neural Network using Bayes Network for handling Uncertain information provided by the user.

Bio Medical Project

Project: Artificial Voice Modulator

-Developed Class I artificial voice modulator

-Designed schematics and state flow diagrams for this device.

-Low power and low noise analogue circuit designed which enchases the battery life of the product.

-Innovative design and added feature like Bluetooth controlled voice.

Extra Activities

-Certification Course in Embedded System Developer from ISM Bangalore.

-Six months training in VLSI academy to understand the CMOS and Fabrication of CHIPS.

-Research paper presented on Space Based Solar Power Transmission using microwave transmission.

-Self-learned Robotic and Artificial Intelligence by Edex

-Paper presentation at Non-conventional energy National conclave held at Mumbai which was organized by RK Institute of Management in Feb 2013.

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