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Vasant Nagar, Karnataka, India
... PERL(beginner level), System Verilog(beginner level) EDA TOOLS Synopsys EDA tools: IC compiler Prime time Cadence EDA tool: Cadence virtuoso Mentor graphics: Modelsim(HDL simulation) FPGA Synthesis Tool: Quartus altera Xilinx Vivado Design Suite. ...
- 2019 Aug 08
Peenya, Karnataka, India
... M.Tech Main Project: “Design and FPGA Implementation of Reversible PROM, Adder & Subtracter using Reversible Decoder” The aim of this work is to design & synthesize of reversible PROM, Half Adder/Subtracter & Full Adder/Subtracter using reversible ...
- 2019 Aug 07
Koramangala, Karnataka, India
... Hardware Systems : NXP ARM Cortex M3 (for Embedded Applications), Basys3 FPGA Board (Processor Based System Design) Technical Skills : Physical Design, Analog & Mixed Signal Circuit Design, STA and PCB Design. Hands on Analysis of different types of ...
- 2019 Aug 07
Vasant Nagar, Karnataka, India
... TECHNICAL EXPERTISE • Design, Development and Testing of hardware-based boards for Defense & Aerospace applications based on Micro controller, FPGA and CPLD’s. • Expertise in Hardware Testing (ATP), Functional Testing of boards (FTP), Integration ...
- 2019 Jul 28
Bangalore, Karnataka, India
... Language : C Platform : Windows 7/XP/8/10 using 8051 microcontroller Description The scope of the project was to design, develop and implementation of an efficient hardware architecture for VGA monitor controllers based on FPGA technology. The ...
- 2019 Jul 20
Vasant Nagar, Karnataka, India
... Pincode-560083 Mobile: +91-954******* LinkedIn ID: https://www.linkedin.com/in/manibhargav-ogirala-23a518172/ Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ...
- 2019 Jul 12
Vasant Nagar, Karnataka, India
... • FPGA generic and specific code (Xilinx & Altera) for memory, clock adaption and JTAG tap. • System configuration in a single definition file. • Example firmware’s using UART and Ethernet. • Test bench included, simulating target software and ...
- 2019 Jul 08
Karnataka, India
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ...
- 2019 Jun 17
Vasant Nagar, Karnataka, India
... SUMMARY OF QUALIFICATIONS: Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using ...
- 2019 Apr 19
Vasant Nagar, Karnataka, India
... Description: Application of the Msp430 in place of FPGA to control the power requirements of a satellite. Centre: ISRO, U.R. Rao Satellite Centre. Achievements: Cleared GATE exam 2019 with a score of 414. Obtained an overall percentile of 81.68 in ...
- 2019 Apr 16