| Resume alert | Resumes 61 - 70 of 139 |
Right now working on a PLL design project
Tempe, AZ
... India Aug’09-May’13 [Electronics and Communication Engineering] GPA: 3.6/4.0 TECHNICAL SKILLS EDA/ Simulation Tool: Cadence Virtuoso, Analog Design Environment (ADE) SoC Encounter, RTL Compiler, Synopsys (Hercules, StarRC, Primetime, Synphony ... - 2018 Nov 15
... India Aug’09-May’13 [Electronics and Communication Engineering] GPA: 3.6/4.0 TECHNICAL SKILLS EDA/ Simulation Tool: Cadence Virtuoso, Analog Design Environment (ADE) SoC Encounter, RTL Compiler, Synopsys (Hercules, StarRC, Primetime, Synphony ... - 2018 Nov 15
Designer Project
Phoenix, AZ
... Processes used: Samsung GF 14LP 14nm finFet Cadence Virtuoso 6.1x and Calibre. Jun 2014 to Crossbar Technologies, Inc. RRam Memory, Contract Layout Designer. Santa Clara, CA Jan 2015 Worked on most of the digital, main project areas. Built many ... - 2018 Nov 14
... Processes used: Samsung GF 14LP 14nm finFet Cadence Virtuoso 6.1x and Calibre. Jun 2014 to Crossbar Technologies, Inc. RRam Memory, Contract Layout Designer. Santa Clara, CA Jan 2015 Worked on most of the digital, main project areas. Built many ... - 2018 Nov 14
Analog and RF circuit design
Tempe, AZ
... 2016-2018 o RF Communication Transceiver Circuit Design (EE524) o Advanced Analog Integrated Circuit Design (EE523) Proficiencies (Software, Skills) Software: Cadence, Advanced Design System (ADS), ADS momentum, Sonnet, HFSS, Microwave Office (AWR), ... - 2018 Nov 12
... 2016-2018 o RF Communication Transceiver Circuit Design (EE524) o Advanced Analog Integrated Circuit Design (EE523) Proficiencies (Software, Skills) Software: Cadence, Advanced Design System (ADS), ADS momentum, Sonnet, HFSS, Microwave Office (AWR), ... - 2018 Nov 12
Accounting, Finance or IT Director, Program Manager, Project Manager
Mesa, AZ, 85208
... Major contributor to the conversion of our project management methodologies to Agile (Kanban and Scrum) from ASAP and Cadence (waterfall) methods along with other improvements to our SDLC processes. Played a key role in two major corporate mergers ... - 2018 Sep 01
... Major contributor to the conversion of our project management methodologies to Agile (Kanban and Scrum) from ASAP and Cadence (waterfall) methods along with other improvements to our SDLC processes. Played a key role in two major corporate mergers ... - 2018 Sep 01
Engineer Design
Phoenix, AZ
... ELECTRONICS, INC, TEMPE, AZ 2002-2018 EVERETT CHARLES TECHNOLOGIES (CIRCUITS), TEMPE, AZ 1997-2002 Senior PCB Designer Skill: Cadence Allegro PCB and PADS PCB High density PCB design layouts that includes Power, Digital, Analog and RF layouts for ... - 2018 Jul 24
... ELECTRONICS, INC, TEMPE, AZ 2002-2018 EVERETT CHARLES TECHNOLOGIES (CIRCUITS), TEMPE, AZ 1997-2002 Senior PCB Designer Skill: Cadence Allegro PCB and PADS PCB High density PCB design layouts that includes Power, Digital, Analog and RF layouts for ... - 2018 Jul 24
C,C++,Java,Servicenow,Javascript
Phoenix, AZ
... Strong Experience with EDA tools – Cadence Design Tools, Synopsys Design Complier, Primetime, IC Compiler, Cadence Encounter, RTL Compiler, Conformal LEC, and Cadence Analog Mixed Signal Design tool Working experience with other tools like Matlab, ... - 2018 Jun 11
... Strong Experience with EDA tools – Cadence Design Tools, Synopsys Design Complier, Primetime, IC Compiler, Cadence Encounter, RTL Compiler, Conformal LEC, and Cadence Analog Mixed Signal Design tool Working experience with other tools like Matlab, ... - 2018 Jun 11
Electrical Engineer (Power Systems)
Tempe, AZ
... TECHNICAL & TRANSFERABLE SKILLS MATLAB PLECS NI Multisim Cadence PSpice Programmable Logic Controller (PLC) C++ Assembly Language Programming Microsoft Excel AutoCAD Trilingual (English, Mandarin Chinese, Malay) LabView - 2018 May 04
... TECHNICAL & TRANSFERABLE SKILLS MATLAB PLECS NI Multisim Cadence PSpice Programmable Logic Controller (PLC) C++ Assembly Language Programming Microsoft Excel AutoCAD Trilingual (English, Mandarin Chinese, Malay) LabView - 2018 May 04
Loan Quality
Tempe, AZ
... Ease Mavent APR Win Spice Works ePosting Rushmar Land Safe Share Point MS Project Citi Frame DRI DARTS/HSSN Jack Henry Mortgage Cadence Lotus Data Link System (DLS) LIS Loan Works Strat Q.Net Quadravision DataVerify Education High School Diploma, ... - 2018 Apr 28
... Ease Mavent APR Win Spice Works ePosting Rushmar Land Safe Share Point MS Project Citi Frame DRI DARTS/HSSN Jack Henry Mortgage Cadence Lotus Data Link System (DLS) LIS Loan Works Strat Q.Net Quadravision DataVerify Education High School Diploma, ... - 2018 Apr 28
Computer Engineering looking for internship in VLSI/ Embedded Systems
Tempe, AZ
... Scripting/Programming Languages: Python, PERL, C/C++, T-SQL, Java Operating Systems: Linux, Windows Software: Cadence Virtuoso, MATLAB Simulink, Xilinx Vivado Design Suite System Edition, Mentor Graphics ModelSim Synopsys Synphony Model Compiler, ... - 2018 Mar 22
... Scripting/Programming Languages: Python, PERL, C/C++, T-SQL, Java Operating Systems: Linux, Windows Software: Cadence Virtuoso, MATLAB Simulink, Xilinx Vivado Design Suite System Edition, Mentor Graphics ModelSim Synopsys Synphony Model Compiler, ... - 2018 Mar 22
Engineer Electrical Engineering
Phoenix, AZ
... Simulation Tools Cadence, Spectre, Matlab, Hspice, Simulink, Vivado, Cadence Encounter, GENESIS2. Layout Tools Cadence Virtuoso Layout Editor. [Nodes: 7nm,28nm,32nm, 180nm, 500nm]. LVS/DRC Tools Calibre, Hercules. WORK EXPERIENCE Product Engineer ... - 2018 Mar 06
... Simulation Tools Cadence, Spectre, Matlab, Hspice, Simulink, Vivado, Cadence Encounter, GENESIS2. Layout Tools Cadence Virtuoso Layout Editor. [Nodes: 7nm,28nm,32nm, 180nm, 500nm]. LVS/DRC Tools Calibre, Hercules. WORK EXPERIENCE Product Engineer ... - 2018 Mar 06