| Resume alert | Resumes 41 - 50 of 139 |
Engineer Software
Gilbert, AZ
... Arduino, Microchip Pic microcontrollers, Cypress FPGA, RaspberryPi, Particle Argon (IOT), Oscilloscope, Multimeter Applications: Cadence (PCB Schematic Designer), Visual Studio(IDE), Matlab, Solidworks, MPLab Programming: Java, C#, C++, C, Python, ... - 2020 Sep 17
... Arduino, Microchip Pic microcontrollers, Cypress FPGA, RaspberryPi, Particle Argon (IOT), Oscilloscope, Multimeter Applications: Cadence (PCB Schematic Designer), Visual Studio(IDE), Matlab, Solidworks, MPLab Programming: Java, C#, C++, C, Python, ... - 2020 Sep 17
Product Design Engineer
Mesa, AZ
... SI Labs, Xilinx, Qualcomm, and Intel embedded software/OS/RF and systems training/certifications Technical team contributor for two Best of CES and three CES Innovation Awards products PROFICIENCIES SolidWorks, Creo, FloTherm, Allegro, Cadence; ... - 2020 Sep 09
... SI Labs, Xilinx, Qualcomm, and Intel embedded software/OS/RF and systems training/certifications Technical team contributor for two Best of CES and three CES Innovation Awards products PROFICIENCIES SolidWorks, Creo, FloTherm, Allegro, Cadence; ... - 2020 Sep 09
Designer Manager
Gilbert, AZ
... Intel Corporation - Intel Custom Foundry and Intel Labs Hillsboro, OR Layout Designer (Intel Contact Employee) 7/2013 – 7/2015 Perform full custom layout for 14nm FinFET process by using Cadence 6.1.6 Using Calibre for LVS/DRC Verifications. Took ... - 2020 Sep 08
... Intel Corporation - Intel Custom Foundry and Intel Labs Hillsboro, OR Layout Designer (Intel Contact Employee) 7/2013 – 7/2015 Perform full custom layout for 14nm FinFET process by using Cadence 6.1.6 Using Calibre for LVS/DRC Verifications. Took ... - 2020 Sep 08
Software Design
Queen Creek, AZ
... ARM CA7 mutli-core, Cadence emulator, eCos, C, ARM assembly language. Pre and post silicon SOC validation of Marvell’s chipset for the Sony play station 4. ATE (Automated Test Envirionment) setup utilizing Marvell’s test equipment. Power management ... - 2020 Aug 28
... ARM CA7 mutli-core, Cadence emulator, eCos, C, ARM assembly language. Pre and post silicon SOC validation of Marvell’s chipset for the Sony play station 4. ATE (Automated Test Envirionment) setup utilizing Marvell’s test equipment. Power management ... - 2020 Aug 28
Electrical Engineer 1
Mesa, AZ
... signal embedded systems •Drafted various parts (ICs, cables, switch boxes) and symbols in Microsoft Visio and Cadence Tools •Increased testing output by 2x when acting as test technician for various projects Quality Assurance Intern, Geco Inc. ... - 2020 Aug 11
... signal embedded systems •Drafted various parts (ICs, cables, switch boxes) and symbols in Microsoft Visio and Cadence Tools •Increased testing output by 2x when acting as test technician for various projects Quality Assurance Intern, Geco Inc. ... - 2020 Aug 11
Design Engineer Engineering
Tempe, AZ
... • Design Tools: Xilinx Vivado & Chipscope, Xilinx ISE 14.6, Innovus, Synopsys Design compiler, Hspice, Modelsim, Matlab, Cadence Virtuoso, Synopsys PrimeTime, IC validator(DRC & LVS) PROFESSIONAL EXPERIENCE RTL Design Engineer, Westghats ... - 2020 Jul 16
... • Design Tools: Xilinx Vivado & Chipscope, Xilinx ISE 14.6, Innovus, Synopsys Design compiler, Hspice, Modelsim, Matlab, Cadence Virtuoso, Synopsys PrimeTime, IC validator(DRC & LVS) PROFESSIONAL EXPERIENCE RTL Design Engineer, Westghats ... - 2020 Jul 16
Engineering Engineer
Phoenix, AZ
... May 2020 Arizona State University, Tempe, AZ 3.40 GPA Technical Skills Design and Applications: Cadence, AutoCAD, MATLAB, ADS Keysight, LabVIEW Programming: Verilog, C++, MIPS, MSVB Other: Microsoft Office, UNIX Internships Texas Instruments 3833 ... - 2020 Jul 07
... May 2020 Arizona State University, Tempe, AZ 3.40 GPA Technical Skills Design and Applications: Cadence, AutoCAD, MATLAB, ADS Keysight, LabVIEW Programming: Verilog, C++, MIPS, MSVB Other: Microsoft Office, UNIX Internships Texas Instruments 3833 ... - 2020 Jul 07
Manager Analyst
Phoenix, AZ
... Assisted Coding (CAC) HIM Reports and Dashboards Upgrades & Optimization Identity®, HIM Chart Deficiency Tracking®, MyChart®, Cadence®, ADT®, Prelude®, EpicCare Inpatient®, EpicCare Phoenix®, and EpicCare Ambulatory® Visio application for workflows ... - 2020 May 28
... Assisted Coding (CAC) HIM Reports and Dashboards Upgrades & Optimization Identity®, HIM Chart Deficiency Tracking®, MyChart®, Cadence®, ADT®, Prelude®, EpicCare Inpatient®, EpicCare Phoenix®, and EpicCare Ambulatory® Visio application for workflows ... - 2020 May 28
Electrical Engineer Design
Tempe, AZ
... India GPA – 7.36/10.0 TECHNICAL SKILLS Programming languages – Python, System Verilog, Perl, C Tools/Simulators/OS – Cadence Virtuoso Schematic and Layout editor, 7nm and 32nm PDK, Mentor Graphics Calibre nmDRC/LVS/PEX, Cadence Spectre, HSPICE, ... - 2020 May 14
... India GPA – 7.36/10.0 TECHNICAL SKILLS Programming languages – Python, System Verilog, Perl, C Tools/Simulators/OS – Cadence Virtuoso Schematic and Layout editor, 7nm and 32nm PDK, Mentor Graphics Calibre nmDRC/LVS/PEX, Cadence Spectre, HSPICE, ... - 2020 May 14
Software Engineer Computer Engineering
Tempe, AZ
... Frameworks: Tensor Flow, OpenCV, Pytorch, Numpy, Scipy, TensorRT • Tools: Xilinx SDx, Xilinx HLS, Xilinx Vivado Design Suite, Cadence IES, Synopsys VCS, Mentor Graphics Questa Sim, MATLAB Simulink, MATLAB Stateflow, Jupyter Notebook, Pycharm, Gem5 • ... - 2020 Apr 02
... Frameworks: Tensor Flow, OpenCV, Pytorch, Numpy, Scipy, TensorRT • Tools: Xilinx SDx, Xilinx HLS, Xilinx Vivado Design Suite, Cadence IES, Synopsys VCS, Mentor Graphics Questa Sim, MATLAB Simulink, MATLAB Stateflow, Jupyter Notebook, Pycharm, Gem5 • ... - 2020 Apr 02