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Right now working on a PLL design project

Tempe, Arizona, United States
November 15, 2018

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+1-480-***-**** PARIJAT BASU **** S Stanley Pl, Apt 115 Tempe, AZ, 85281, USA Recent Graduate from Arizona State University with one year of experience seeking full-time opportunities in the fields related to Analog/ Mixed-Signal Design, Verification and Validation. Visa Status: F1 (OPT). Available to start immediately. EDUCATION

Master of Science, Arizona State University, USA Jan’16-Dec’17

[Electrical Engineering] Specialization in Electronic and Mixed-Signal Circuit Design GPA: 3.2/4.0

Bachelor of Technology, West Bengal University of Technology, India Aug’09-May’13

[Electronics and Communication Engineering] GPA: 3.6/4.0 TECHNICAL SKILLS

EDA/ Simulation Tool: Cadence Virtuoso, Analog Design Environment (ADE) SoC Encounter, RTL Compiler, Synopsys

(Hercules, StarRC, Primetime, Synphony Model Compiler), Simulink, HSPICE, Spectre, LTSPICE, Calibre, Xilinx ISE

HDL/ Scripting/ Programming: VHDL, Verilog, System Verilog, Verilog-A, Python, Shell Scripting, TCL, C, MATLAB, Java

Coursework: • Analog IC Design • Advanced Analog IC Design • Digital Systems and Circuits • VLSI Design • Advanced Power Electronics • Oversampling Sigma Delta ADC/ DAC • Semiconductor Characterization • Digital Signal Processing

Concepts: • Bandgap references, charge pumps, feedback and oscillators, comparator, integer-N and fractional-N PLLs

• Signal and power integrity concepts • Semiconductor device physics PROFESSIONAL EXPERIENCES

Lab Assistant, Arizona State University, Tempe US Feb’18-present

• Designing 1.6GHz PLL with loop bandwidth of 1MHz for 1.8V supply on 0.3um TSMC process with voltage-controlled oscillator (VCO) tuning range of 1.0 to 3.5 GHz • Simulation of phase noise and estimation of PLL loop parameters

Graduate Teaching Assistant, Arizona State University, Tempe US Aug’17-Dec’17

• Assisted students in various analog and digital design projects • Attended several recitation classes on analog design

• Evaluated assignments and projects for the courses Circuits-II (EEE-202) and Analog & Digital Circuits (EEE-335)

Graduate Research Assistant, Arizona State University, Tempe US May’16-Jul’16

• Developed hardware in Verilog/VHDL and MATLAB for efficient mapping of DSP algorithms on Xilinx FPGA (Virtex-7) and ASIC • Proposed a hardware-accelerated gesture recognition system with higher energy efficiency than existing ones

Associate System Engineer, IBM, India Dec’14-Dec’15

• Created data models of different business wings for a leading airline • Tested metadata modules in SQL and SAP HANA

• Conducted trainings for the new hires and involved in weekly client interactions demonstrating updates and reports ACADEMIC PROJECTS

Two Stage RC Compensated Operational Amplifier (Op-Amp) (Cadence ICFB, Spectre)

• First stage: differential to single-ended amplifier; second stage: telescopic cascode • Achieved open loop gain of 89dB, phase margin of 68.78 and GBW of 10.37 MHz from frequency-response • RC tuning for lead compensation

Single Ended NMOS Input Folded Cascode Amplifier with Class-AB Output Buffer (Cadence ICFB, Spectre)

• Biasing with β-multiplier technique • Achieved gain margin of 19.4dB, phase margin of 64 ,open loop DC gain of 102.8 dB and met design specs like GBW, CMRR, PSRR, THD, output swing and slew rate for a 3V supply and 2mW power

Symmetric Operational Transconductance Amplifier (OTA) Design and Layout (TSMC 0.3u) (Cadence ICFB, Spectre)

• Biasing with β-multiplier technique • Achieved a DC gain of 60dB, measuring the input referred noise as 9.291nV/sqrt

(Hz) with a max power of 1.5mW for a 2.5V supply over 0.5V common-mode voltage of 1.5V • Custom layout (in TSMC 0.3u) using common-centroid and interdigitization techniques for matching and performed layout verification successfully

Third Order Continuous-Time Delta-Sigma Data Converter (MATLAB, Simulink, Cadence Virtuoso IC6)

• Implemented the discrete time system, validated stability for each filter and performed noise analysis • Modeled equivalent continuous time system using impulse invariant method and designed quantizer with 8-bit register-based flash and DAC with active-RC architecture • Achieved SNR of 79.23 dB at OSR 30, sampling rate 30MHz, 500KHz bandwidth

Low Dropout Regulator (LDO) (Cadence ICFB, Spectre)

• PMOS pass transistor based LDO for a Voltage regulation of 2.3V • A single stage telescopic double-cascode differential amplifier with an open loop gain of 60dB selected for error amplifier comparing reference and feedback voltage

Coupled-Inductor and Diode-Capacitor DC-DC Converter for Power Management Applications (MATLAB, PLECS)

• Modeled and simulated a high efficiency, high step–up DC-DC converter • Improved the conventional buck converter with a better source side power factor with reduced harmonics, improved voltage conversion ratio at the load side

Standard Cell Library (Synopsys 32nm PDK & ARM 7nm PDK with FinFETs) (Cadence Virtuoso IC6, HSPICE)

• Schematic and Layout of the standard cells: NANDX2, NORX3, 8-bit Modulo Adder (32nm) and MUXx2, SDFLx3 (7nm)

• Layout verification (DRC and LVS) and design trade-off for performance and area • Measured the parameters such as propagation delay, rise time and fall time • Performed parasitic extraction • Generated the netlist and the testbench in HSPICE to perform pre-layout and post-layout static timing analysis

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