Haviesh Kosuru

**** * ******* **** *******, Phoenix, AZ 972-***-**** ac5tv9@r.postjobfree.com

Objective

To obtain a Fulltime position in Electrical and Computer Engineering field related to Digital/Analog/Mixed-Signal (FPGA/ASIC) Design and Verification technology.

Education

University of Bridgeport - May 2017

MS – Electrical & Computer Engineering, GPA 3.6

Jawaharlal Nehru Technological University - June 2015

BS - Electronics and Communication Engineering, GPA 3.5

Professional Summary & Skillset

Working as Infra developer for DISCOVER FINANCIAL SERVICES.

Experience in Integrated Circuit design languages like Verilog, VHDL, System Verilog, RTL coding for high level Logic Synthesis, Electromagnetics, Transmission lines and Digital Signal Processing.

Proficiency in C, C++, Java Programming languages.

Fluent in Tcl, Perl, Python, Ruby and Shell scripting languages.

Strong Experience in writing UPF/CPF for low power Design.

Strong Experience in Advance Static and Formal Verification Techniques and tools like VCS, Modelsim, AMS verification, DFT

Strong Experience in RTL power estimation & optimization, STA, and timing closure.

Strong Experience with EDA tools – Cadence Design Tools, Synopsys Design Complier, Primetime, IC Compiler, Cadence Encounter, RTL Compiler, Conformal LEC, and Cadence Analog Mixed Signal Design tool

Working experience with other tools like Matlab, LabVIEW and Altera Quartus Prime and SPICE.

Proficiency in MS office, Unix, and Linux operating systems.

Certifications – Cisco Certified Network Associate (CCNA), PCB Design Engineer (EFY), ServiceNow System Administrator.

Work Experience

Clint: Discover Financial Services Infra Developer

Cognizant Technology Solutions (August 2017 – Present)

Integrated ServiceNow with Middleware WebSphere, Oracle Database, Jenkins and Apache Tomcat.

Using Jenkins Created Jobs like Restart, App deployment, Custom Properties, Failed ping events, JVM Heap, JVM app Dynamics, etc.

Working on SERVICENOW IT OPERATIONS MANAGEMENT(ITOM) applications.

Obtained ITIL v3 certification and ServiceNow Certified System Administration.

Partner Support Engineer

UBER Technologies INC, Hyderabad, India (July 2015- November 2015)

Worked in Customer support by solving Wireless Specific issues (802.11a/x) and Worked on application support on UBER database.

Worked with the data science team to perform in-depth statistical data analysis of the public transport networks across different cities in India.

Design Intern

Defense Electronics Research Laboratory, Hyderabad, India (January 2015 – June 2015)

Worked on project “Wideband waveform generation using SDR platform”.

Designed a fast switching direct digital frequency synthesizer (One of the application of RF Transceiver) for jammer system, the carrier frequencies thus generated by the synthesizer are to be used in different modulation techniques. Worked with test engineers to validate and debug Chip and also supported in STA checks.

Core Duties Include: Test bench implementation and Verification.

Tools used: Matlab, Xilinx Virtex-7 FPGA family, Spartan-7, FMC150, Spectrum analyzers, oscilloscopes, logic analyzers, network analyzers and Frequency synthesizer.

Project Experience:

Design of 32-bit RISC Processor: Implemented a 16-bit RISC microprocessor based on a simplified version of the MIPS architecture. The processor has 16-bit instruction words and 16 general purpose registers. Implemented Instruction set architecture and then Followed ASIC DESIGN FLOW. Where it is coded using Verilog RTL in Altera, tested using VCS and Implemented Layout and design gone through floorplan, placement, Static Timing analysis, clock tree synthesis and routing. designed 16-bit Comparator using Verilog and simulated using Modelsim and Created Layout using Cadence Design Tool.

•Implementation of 3 stage pipelined Memory Register RISC Processor: Followed ASIC DESIGN FLOW. Using FSM Verilog HDL is implemented, Simulated with Design Compiler to generate Gate Level Netlist. The Netlist is taken through floorplan, placement, Static Timing analysis checks (Pre layout and post layout STA, formal verification), clock tree synthesis and routing using IC Compiler.

•Worked on ARM-7 Mobile phone communication with Microcontroller, ARM-7 Vehicle location using GSM / GPS and ARM-7 Home Automation using Bluetooth. Responsibilities: Writing code in Embedded C on Keli, Loading the Code into LPC2148 and Debugging the Code and Verifying the test conditions.

•Worked on TMS320C6713 DSK board, Writing the C programming code (software) in Code composure studio and debugging it using DSP board (Hardware) and Verifying outputs using Spectrum Analyzer, Oscilloscope, and Frequency Synthesizer

Achievements

“Minimum Leakage Vector using Genetic Algorithm”, Paper Publication in International Journal of Trend in Research and Development (IJTRD), ISSN: 2394-9333.

University of Bridgeport Academic Scholarship, Dean’s List 2016-Present.

Represented University College for Table Tennis, led the team and won Volley Ball & Cricket Tournaments.

Outstanding Achievement Award for Best Customer support for UBER IN NOVEMBER 2015.

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