Christopher G. Clevenger

Email: ac7ozv@r.postjobfree.com

Telephone 602-***-**** (m)

OBJECTIVE: Seeking a position as a layout designer.

Jan 2015 to Advanced Micro Devices Global Design Group, Contract Layout Designer Sunnyvale, CA

Jul 2015 Built Crystal Oscillator Pad. Processes used: Samsung GF 14LP 14nm finFet

Cadence Virtuoso 6.1x and Calibre.

Jun 2014 to Crossbar Technologies, Inc. RRam Memory, Contract Layout Designer. Santa Clara, CA

Jan 2015 Worked on most of the digital, main project areas. Built many blocks including but not

limited to: x/y predecs, timers, pretimers, regmap, regout, rdn, fstm and wrtckt.

Top level routing and verification. Tools used: Cadence VXL 6.1.5, PVS and

Assura LVS/DRC.

Apr 2010 to Advanced Micro Devices GPU analog group, Contract/Direct Layout Designer Sunnyvale, CA

Feb 2013 Worked on a diverse range of designs for production and test chips

Processes used: 28nm and below. Cadence Virtuoso 6.1x and Calibre.

2008/2009 Freescale, Inc. Wireless Connectivity Operations, Contract Layout Designer Tempe, AZ

Worked on full custom RF/Analog production and test chips. Built Sigma Delta, VCO

and other blocks, also top level routing and verification. Process used TSMC .18u

Deep N-Well.Tools used: Cadence VXL and Composer. Calibre LVS/DRC

2006 – 2007 Intel, Inc. Contract Layout Designer Chandler, AZ

Layout work on full custom power management IC’s w/multiple switching regulators.

Built bandgap, clock dist. SAS/SATA transceiver and other blocks. Processes used:

65 and 90 nm. Tools used: Cadence VXL and Composer, Avant! LVS/DRC,

and in-house tools.

2005 – 2006 P.A.Semi, Inc. Contract Layout Designer Santa Clara, CA

Layout of SoC microprocessor data path and misc blocks.

Tools used: Mentor IC Studio, Calibre LVS/DRC and in-house tools.

2005 ATI Technologies, Inc. Contract Layout Designer Santa Clara, CA

Layout work on high speed mixed signal chips. Worked with phase

Interpolators, idle detectors and other blocks.

Tools used: Cadence, Calibre LVS/DRC and Assura.

1998 – 2003 Silicon Graphics, Inc. Contract Layout Designer Mountain View, CA

Trex project Layout and rework of microprocessor blocks.

Tools used: Virtuoso, Calibre LVS/DRC and Dracula

1998 Intel. Contract Layout Designer Chandler, AZ Merced project. Layout of microprocessor blocks.

Tools used: Intel in-house layout and verification.

1997 – 1998 Silicon Graphics, Inc. Contract Layout Designer Mountain View, CA Trex project. Layout and rework of microprocessor blocks.

Tools used: Virtuoso, Calibre LVS/DRC and Dracula

1996 – 1997 Silicon Graphics, Inc. Contract Layout Designer Mountain View, CA Beast project. Layout and rework of microprocessor blocks.

Tools used: Virtuoso, Dracula, Avante, and Concept

1994 – 1996 Intel. i960 uP Design Group, Contract Layout Designer Chandler, AZ

Layout of microprocessor and test chips. Worked with memory,

data path and pad cells. Tools used: Intel in-house layout and verification.

Also used, Dracula LVS/DRC.

1990 – 1994 Motorola. High Performance uP Division, Direct Mask Designer Chandler, AZ

Responsible for cell layout, chip level reroute, Mask shop prep and

Full chip DRC. Tools used: Cadence, Cats, Calma and Vax.

EDUCATION:

Mesa Community College, Mesa, AZ Cadence Design Systems, Inc., San Jose, CA

Associate of Applied Science Degree Candidate Classes include: Design Framework Environment

Electro-Mechanical Drafting Layout Editor and Advanced Layout Accelerators

References and additional information available upon request.

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