| Resume alert | Resumes 141 - 150 of 513 |
RF Engineer
Union City, CA
... Solar Controller, DTMF, Voice IC Technical Skills Programming Languages: C, C++,Python(beginner) Software: MATLAB, Arduino IDE, Cadence Virtuoso, Multisim, Atmel Studio, LaBView RF Equipment - Signal generator, Oscilloscope, PLC, Spectrum Analyzer, ... - 2018 Jan 15
... Solar Controller, DTMF, Voice IC Technical Skills Programming Languages: C, C++,Python(beginner) Software: MATLAB, Arduino IDE, Cadence Virtuoso, Multisim, Atmel Studio, LaBView RF Equipment - Signal generator, Oscilloscope, PLC, Spectrum Analyzer, ... - 2018 Jan 15
Verilog, Perl, Digital IC design, FPGA/ASIC design, Physical Design
San Jose, CA
... Xilinx ISE, MATLAB • EDA Tools: Synopsys – HSpice, PrimeTime, Design Compiler, IC compiler, VCS, Custom Compiler, ESP-CV Cadence – Virtuoso Schematic and Layout editor, Encounter, Conformal, Innovus Mentor – Modelsim, Calibre • Operating System: ... - 2018 Jan 11
... Xilinx ISE, MATLAB • EDA Tools: Synopsys – HSpice, PrimeTime, Design Compiler, IC compiler, VCS, Custom Compiler, ESP-CV Cadence – Virtuoso Schematic and Layout editor, Encounter, Conformal, Innovus Mentor – Modelsim, Calibre • Operating System: ... - 2018 Jan 11
Verilog, System Verilog, SV Assertions, Physical Design, DFT
Campbell, CA
... SKILLS • Programming Languages : Proficiency Level Verilog, C : System Verilog, System Verilog Assertions: VHDL, PERL : Linux Shell Scripting, X86 Assembly : • Verification Methodologies: UVM • Design Tools: Cadence Virtuoso, Cadence NC Launch, ... - 2018 Jan 07
... SKILLS • Programming Languages : Proficiency Level Verilog, C : System Verilog, System Verilog Assertions: VHDL, PERL : Linux Shell Scripting, X86 Assembly : • Verification Methodologies: UVM • Design Tools: Cadence Virtuoso, Cadence NC Launch, ... - 2018 Jan 07
Design Engineer Professional Experience
San Jose, CA
... Expertise includes Place & Route design automation utilizing ICC & TCL scripts for ASIC physical implementation, automated design library/collateral view generation using ICC and Cadence Virtuoso, block-level and chip-level layout verification using ... - 2017 Dec 21
... Expertise includes Place & Route design automation utilizing ICC & TCL scripts for ASIC physical implementation, automated design library/collateral view generation using ICC and Cadence Virtuoso, block-level and chip-level layout verification using ... - 2017 Dec 21
ASIC Verification Engineer, NVIDIA
San Jose, CA, 95134
... C++ STL, MPI, OpenGL, pThreads, Linux, GNU Toolchain (gdb, awk, sed, Make, etc.) Tools CUDA, ns-2, pSpice, EagleCAD, GNU Radio, Cadence Virtuoso Design and Verification VCS, Verdi, ModelSim, UVM, DPI-C, PLI, C-models for Verification, Fullchip/SoC ... - 2017 Dec 12
... C++ STL, MPI, OpenGL, pThreads, Linux, GNU Toolchain (gdb, awk, sed, Make, etc.) Tools CUDA, ns-2, pSpice, EagleCAD, GNU Radio, Cadence Virtuoso Design and Verification VCS, Verdi, ModelSim, UVM, DPI-C, PLI, C-models for Verification, Fullchip/SoC ... - 2017 Dec 12
Design Electrical Engineering
San Jose, CA
... MPLAB IDE, LTpower Play, multi-meter, Optical Spectrum analyzer, Logic analyzer Electronic Design Tools: Synopsys VCS, NCVerilog, Design Compiler, Altera Quartus II, Cadence Virtuoso, Cadence Encounter, Cadence Allegro Physical Viewer, ModelSim. ... - 2017 Dec 06
... MPLAB IDE, LTpower Play, multi-meter, Optical Spectrum analyzer, Logic analyzer Electronic Design Tools: Synopsys VCS, NCVerilog, Design Compiler, Altera Quartus II, Cadence Virtuoso, Cadence Encounter, Cadence Allegro Physical Viewer, ModelSim. ... - 2017 Dec 06
Program Manager, UX Designer
San Jose, CA
... - Running XRC, XCC, and Power Extrac on, by using the extrac on program in cadence, helped the circuit engineers with changes in circuits. - Knowledge of device op miza on, minimizing parasi cs, component matching, including techniques to minimize ... - 2017 Dec 02
... - Running XRC, XCC, and Power Extrac on, by using the extrac on program in cadence, helped the circuit engineers with changes in circuits. - Knowledge of device op miza on, minimizing parasi cs, component matching, including techniques to minimize ... - 2017 Dec 02
Engineer Manager
San Jose, CA
... • Jan 2002 – July 2003 Senior Architect, Cadence Design Systems, Inc.. Austin, TX Telecommuting from Austin. Working on the interface between Open Access and ‘First Encounter’ floorplanner. Patent awarded for Genesis database technology # 6,529,913. ... - 2017 Nov 28
... • Jan 2002 – July 2003 Senior Architect, Cadence Design Systems, Inc.. Austin, TX Telecommuting from Austin. Working on the interface between Open Access and ‘First Encounter’ floorplanner. Patent awarded for Genesis database technology # 6,529,913. ... - 2017 Nov 28
Electrical Engineering Design
Cupertino, CA
... Control aspects of the RAM were verified using system Verilog assertions TECHNICAL SKILLS Programming Languages: Verilog, Perl, Python, C, C++, UVM, System Verilog Tools Used: Vivado HLS, Synopsys VCS, Formality, Cadence Virtuoso, Mentor Graphics IC ... - 2017 Nov 22
... Control aspects of the RAM were verified using system Verilog assertions TECHNICAL SKILLS Programming Languages: Verilog, Perl, Python, C, C++, UVM, System Verilog Tools Used: Vivado HLS, Synopsys VCS, Formality, Cadence Virtuoso, Mentor Graphics IC ... - 2017 Nov 22
Manager Designer
San Jose, CA
... & Flex Cable, Using Cadence Allegro 16.6. OCZ Storage Solutions, San Jose, CA (Contract) Dec 14 – Mar 15 CAD/PCB Librarian & Layout Designer Responsibilities: 1Maintain ownership of CAD libraries and insure synchronicity, Design Layout of 4 - 10 ... - 2017 Oct 31
... & Flex Cable, Using Cadence Allegro 16.6. OCZ Storage Solutions, San Jose, CA (Contract) Dec 14 – Mar 15 CAD/PCB Librarian & Layout Designer Responsibilities: 1Maintain ownership of CAD libraries and insure synchronicity, Design Layout of 4 - 10 ... - 2017 Oct 31