Manager Designer
Resume:
STEFAN NAJMI
ac2179@r.postjobfree.com
OBJECTIVE:
PCB Design Layout Engineering & CAD Libraries
EXPERIENCE SUMMARY:
1Over 14 years of extensive experience as a PCB designer/Layout designer with leading companies.
2Over 12 years of experience working with Allegro and its constraint manager.
3Over 7 years of experience with RF PCB’s.
4Working familiarity with Orcad capture schematic.
5Working familiarity Using PCIe, and other expansion card and interface connectors.
6Working experience Using proper layout technique for DDR2 - DDR4 termination guide lines.
7Extensive experience with Using microvias, multilayer PCB, CAD etc
8Assisting engineers in the design and development of complex and detailed layouts of printed circuit boards upon EMI / EMC / DFM compliance.
9Experience with design Layout of high-speed Analog Digital Processor, RF, Power Supply, and Sensor PCB's & Flex cable upon calculating of signal impedance for micro-strip and strip line & differential pair within Allegro & PADS, Orcad, Protel 99SE.
TECHNICAL SKILLS:
1CADENCE ALLEGRO 16.6, 16.3 …/ VIRTUOSO
2PADS - POWER PCB (Mentor 9.4)
3ORCAD LAYOUT & SCHEMATIC CAPTURE / CIS (16.6…..10.0)
4PROTEL 99SE/ DXP, CAMTASTIC
5VIEWLOGIC (Mentor)
6UNIX,WIN NT,95,98
7QUICK ADJUSTMENT TO OTHER CAD TOOLS
PROFESSIONAL EXPERIENCE:
TDK (CONTRACT), SAN JOSE, CA AUG/ 17- PRESENT
CAD/PCB LIBRARIAN & LAYOUT DESIGNER
RESPONSIBILITIES:
1 MAINTAIN OWNERSHIP OF CAD LIBRARIES AND INSURE SYNCHRONICITY AND MIGRATION FROM PADS TO CADANCE ALLEGRO 17.2.
Intel Corp. Santa Clara, CA (Contract) April 2015 – July 17
Senior PCB Designer
Responsibilities:
1Design layout & modification of RF & Analog Digital high speed board & up to 12 layer. & Flex Cable, Using Cadence Allegro 16.6.
OCZ Storage Solutions, San Jose, CA (Contract) Dec 14 – Mar 15
CAD/PCB Librarian & Layout Designer
Responsibilities:
1Maintain ownership of CAD libraries and insure synchronicity, Design Layout of 4 - 10 Layer Analog & Digital High-speed Boards, including multiple interface devices such as PCIE connector, Differential pair routing nets and DDR’s, using Cadence Allegro 16.6, & Orcad.
Cephasonics, Santa Clara, CA (via Oxford Assoc) (Contract) Jan 13 – Aug 14
Senior PCB Layout Designer
Responsibilities:
2Design Layout of 14 - 22 Layer Analog & Digital High-speed Boards, creating/maintaining library, using Cadence Allegro 16.6, Orcad CIS.
3Worked on RF PCB Ultrasound technology products (capturing image, combining image, power board)
4Managing all aspects of physical, electrical design rules using Cadence/Allegro constraint manager.
Aptina Inc, San Jose, CA (via Oxford Assoc) (Contract) May 12 – Sep 12
Senior PCB Layout Designer
Responsibilities:
1Design Layout of 4 - 12 Layer Analog & Digital Boards, creating/maintaining library, using Cadence Allegro 16.3, Orcad CIS & PADS 9.4.
2Managing all aspects of physical, electrical design rules using Cadence/Allegro constraint manager.
Inphi Inc., Santa Clara/ Westlake village, CA (Contract) July/11-May/12
PCB CAD Librarian
1Involved in designing RF PCB and impedance capture.
2Design Layout of Multi Layer PCB, Creating and Maintaining Golden Library in Cadence Allegro 16.3
3Managing all aspects of physical, electrical design rules using Cadence/Allegro constraint manager.
Stretch, Inc., Sunnyvale, CA (Contract) Oct/10 – Jan/11
Senior PCB Layout Designer
Responsibilities:
1Design Layout of multi Layer PCB.upon using Cadence Allegro 16.3.
2Managing all aspects of physical, electrical design rules using Cadence/Allegro constraint manager. Creating and Maintaining Library footprints in Cadence Allegro.
Wohler Technologies, Inc, Hayward, CA Jun/07 – Nov/09
Senior PCB Layout Designer
Responsibilities:
1Design Layout of multi Layer Digital and analog Board for Broad Casting Industries.
2Involved in designing Broadcasting RF PCBs and worked on image transfer signals and image.
3Within Allegro 16. Orcad . Creating and Maintaining Library footprints in Cadence Allegro.
Nano Nexus Inc. San Jose, CA Jan/07 – Mai/07
Senior PCB Layout Designer
Responsibilities:
1Managing Design layout process for Test Board up to sixty layers.
2Within Allegro 15.2. Creating and Maintaining Library footprints in Cadence Allegro.
3Managing all aspects of physical, electrical design rules using Cadence/Allegro constraint manager.
LATHROP ENGINEERING Inc, San Jose, CA Sep/05 – Nov/06
Senior PCB Designer
Responsibilities:
1Design Layout of PCB for Bio Medical industries.
2Using Orcad Layout and capture schematic.
Intel Corp. Portland (Kelly Services…. wwid10981977), OR Jan/05 – 04/05
Senior PCB Designer
Responsibilities:
2Design layout & modification of Analog Digital highspeed board up to 24 layer
3Within Allegro 15. Creating and Maintaining Library footprints in Cadence Allegro and Concept.
NEW HORIZONS, Saratoga, CA 02/04 - 11/04
Senior CADD Consultant
Responsibilities:
1Assisting Engineer upon their needs for Design Layout & CADD
2Within Allegro 14.2.
PELCO Inc. Clovis, CA 06/03- 01/04
Senior PCB Designer
Responsibilities:
1Design Layout of highspeed Analog Digital Processor, RF, Power Supply, and Sensore PCB's with signal impedence action for microstrip and strip differential pair within Allegro & Protel 99SE
LOCO LAB Inc. San Jose, CA 06/02- 10/02
Senior PCB Designer
Responsibilities:
1Designing 12 layer Analog Digital highspeed Processor Board for video systems with signal impedence action for differential pair, BGA's
2FPGA's within Allegro constraint, Orcad Capture
PEMSTAR Pacific Consultants Inc, San Jose, CA 03/01- 05/02
Senior PCB Designer
Responsibilities:
1Designing up to 12 layer Analog Digital highspeed & RF PCB containning Processor and Powersupply Board and GPS System for LandWarrior Project.
2Quoting jobs upon the company guidelines.PADS, Allegro 13.6 Orcad Layout and Capture 9.7
Intel Corp. San Jose (Kelly Services), CA Jan - Feb/01
Senior PCB Designer
Responsibilities:
1Editing Analog Digital highspeed 10 layer PCB Board including BGA's SDRAM's FPGA's within Allegro constraint,Orcad
3dfx Interactive inc. San Jose, CA Sep - Dec/00
Senior PCB Designer
Responsibilities:
2Designed highspeed PCB's within Cadence Allegro 13.6 environment.
Xpeed Inc, Santa Clara, CA April - Sep/00
PCB DESIGNER
Responsibilities:
3Designed PCB Board within Cadence Allegro and Concept schematic
CABLETRON SYSTEM, Santa Clara, CA Jan - April/00
PCB DESIGN & LIBRARIAN
DDI/DESIGN PLUS LLC, MILPITAS, CA 1998 - 1999
PCB DESIGNER & Librarian
EDUCATION:
1Mechanical Engineering
1984 – 1988,
FH AACHEN UNIVERSITY, AACHEN, GERMANY
22004 – 20, Valley Technical Institute, San Jose, CA
Aricent/Intel
Bala Murugan
Engineering Manager
Santa Clara, CA
Phone
References of past superviso
Bala Murugan
Aricent/Intel
ac2179@r.postjobfree.com
Cephasonics
Bob Uvacek
Director of Engineering
Location
Santa Clara, CA
ac2179@r.postjobfree.com
Interviews you are currently pursuing:
Contact this candidate