| Resume alert | Resumes 121 - 130 of 512 |
Engineer Electrical
San Jose, CA
... Experienced and expert knowledge of most design tools including Cadence Concept schematic capture, Allegro PCB layout tool. Expertise in high speed board design including component selection, schematic capture, PCB layout. Experienced and designed ... - 2018 May 07
... Experienced and expert knowledge of most design tools including Cadence Concept schematic capture, Allegro PCB layout tool. Expertise in high speed board design including component selection, schematic capture, PCB layout. Experienced and designed ... - 2018 May 07
Engineer Software
Santa Clara, CA
... CADENCE DESIGN SYSTEM, San Jose, CA 2010 – 2011 Senior Member of Consulting Staff Software developer in the Spectre team. Built Python based circuit characterization flow tool for TSMC by utilizing direct Spectre API calls, thereby improved ... - 2018 Apr 12
... CADENCE DESIGN SYSTEM, San Jose, CA 2010 – 2011 Senior Member of Consulting Staff Software developer in the Spectre team. Built Python based circuit characterization flow tool for TSMC by utilizing direct Spectre API calls, thereby improved ... - 2018 Apr 12
PCB Layout Designer
San Jose, CA
... Qualcomm – PCB Layout 2011/11 –2016/02 Import nets from Orcad CIS or Cadence Concept HDL to Cadence Allegro, create board outline, parts placement, routing, constraints setup, implement DFA/emn/emp mechanical constraint for high speed multi-layer ... - 2018 Apr 06
... Qualcomm – PCB Layout 2011/11 –2016/02 Import nets from Orcad CIS or Cadence Concept HDL to Cadence Allegro, create board outline, parts placement, routing, constraints setup, implement DFA/emn/emp mechanical constraint for high speed multi-layer ... - 2018 Apr 06
Design Electrical Engineering
Santa Clara, CA
... • Designed and simulated schematic in Cadence with IBM 0.13μm 8HP BiCMOS technology kit as well as layout design and simulation. • Used Monte Carlo Distribution on key parameters (width/length/number of gate figures and etc.) to discover the effects ... - 2018 Mar 29
... • Designed and simulated schematic in Cadence with IBM 0.13μm 8HP BiCMOS technology kit as well as layout design and simulation. • Used Monte Carlo Distribution on key parameters (width/length/number of gate figures and etc.) to discover the effects ... - 2018 Mar 29
Design Electrical Engineering
San Jose, CA
... PROJECTS 8-bit Asynchronous Counter – Cadence Virtuoso & Encounter Design was based on the TSMC 180nm process, and satisfied DRC, LVS, and QRC checks. A supply voltage of 0.9 Volts was used and the timing spec of 1MHz was achieved. Achieved a 40% ... - 2018 Mar 29
... PROJECTS 8-bit Asynchronous Counter – Cadence Virtuoso & Encounter Design was based on the TSMC 180nm process, and satisfied DRC, LVS, and QRC checks. A supply voltage of 0.9 Volts was used and the timing spec of 1MHz was achieved. Achieved a 40% ... - 2018 Mar 29
Design Engineer
San Jose, CA
... : AMBA, AHB, APB, AXI4, AXI4-Lite, CAN, SPI, UART, I2C, Ethernet EDA Tools : Synopsys VCS, Design Compiler, Design Vision, Cadence Virtuoso, Xilinx ISE, Vivado, Altera Quartus, Other Skills : ASIC Design, RTL design, Design Synthesis, Static Timing ... - 2018 Mar 13
... : AMBA, AHB, APB, AXI4, AXI4-Lite, CAN, SPI, UART, I2C, Ethernet EDA Tools : Synopsys VCS, Design Compiler, Design Vision, Cadence Virtuoso, Xilinx ISE, Vivado, Altera Quartus, Other Skills : ASIC Design, RTL design, Design Synthesis, Static Timing ... - 2018 Mar 13
Design Engineer
San Jose, CA
... SRAM Design using 45nm technology New York University August 2016 – December 2016 • Developed a 64 Bit SRAM using 45nm technology and 800mv supply, on Cadence Virtuoso [NCSU 45nm library] in a team of four. • Implemented the SRAM Cell with read ... - 2018 Mar 08
... SRAM Design using 45nm technology New York University August 2016 – December 2016 • Developed a 64 Bit SRAM using 45nm technology and 800mv supply, on Cadence Virtuoso [NCSU 45nm library] in a team of four. • Implemented the SRAM Cell with read ... - 2018 Mar 08
Electrical Engineer State University
Union City, CA
... and Equipment: Oscilloscope, Function Generators, Digital Multi-Meter, 3D Printers, Electric Soldering Iron, DC power supply EDA Software: LT Spice, PSpice, DipTrace, PCB layout, Xilinx Design Suite 14.7, Cadence, LabVIEW, SolidWorks, AutoCAD. ... - 2018 Mar 01
... and Equipment: Oscilloscope, Function Generators, Digital Multi-Meter, 3D Printers, Electric Soldering Iron, DC power supply EDA Software: LT Spice, PSpice, DipTrace, PCB layout, Xilinx Design Suite 14.7, Cadence, LabVIEW, SolidWorks, AutoCAD. ... - 2018 Mar 01
Engineer Electrical Engineering
San Jose, CA
... Dates Attended: 08/1995 to 06/1999 EMPLOYMENT EXPERIENCE Cadence Design Systems, San Jose, California 07/2011 to Present Principal Configuration Management Engineer (Formerly: Member of Consulting Staff) Responsibilities: SCM build/release lead for ... - 2018 Feb 26
... Dates Attended: 08/1995 to 06/1999 EMPLOYMENT EXPERIENCE Cadence Design Systems, San Jose, California 07/2011 to Present Principal Configuration Management Engineer (Formerly: Member of Consulting Staff) Responsibilities: SCM build/release lead for ... - 2018 Feb 26
Electrical Engineer Engineering
San Jose, CA
... • Proficient at Cadence Orcad and Altium PCB Design tools. • Skilled at problem-solving related to the design, fabrication, and assembly. • Hands on experience with schematic simulation tools OrCAD, TINA. • Able to understand and apply best ... - 2018 Feb 25
... • Proficient at Cadence Orcad and Altium PCB Design tools. • Skilled at problem-solving related to the design, fabrication, and assembly. • Hands on experience with schematic simulation tools OrCAD, TINA. • Able to understand and apply best ... - 2018 Feb 25