ADITYA VENKATRAMAN

ac3f4w@r.postjobfree.com

669-***-****

OBJECTIVE

Actively seeking full time opportunities in the field of Digital VLSI Design, Verification and testing which will allow me to utilize my knowledge and make my effective contribution to the continued growth and success of the organization. WORK EXPERIENCE

ASIC Design Engineer(Contractor) at Scalable Systems Research Labs Inc. (Sept’16-May’17)-(Sept’17-Present)

• Currently working on design and verification of endpoint block of PCI express gen3 using Verilog and UVM respectively

• Designed and verified 1024 x 1024 Network on chip which tremendously improved speed of the neural net Coprocessor R&D Engineering intern at Synopsys Inc. (June ’17- August’17)

• Worked on running library characterization and finding solutions to problems in characterization.

• Successfully worked on modeling of timing, power and HDL views, as well as datasheets with the description of the cells in each library.

ACADEMIC PROJECTS

• 32--bit MIPS processor Fall 2014

Designed a single cycle datapath for R, I and J type of instruction formats and implemented it using Verilog. The project was done using Synopsys VCS. This design improved speed and reduced area of the processor.

• 16x16 Internet switch Fall 2014

Designed a switch using Verilog and synthesized it to gate level using lsi_10k library. This design improved speed as two devices could communicate directly via the switch without any need to access the memory.

• UVM based verification-AHB bus protocol. Spring 2015 Worked on System Verilog UVM test bench and infrastructure for verifying AHB bus protocol functionality.

• FPGA Implementation of Road Lane Detection (C to Verilog : High Level Synthesis) Winter 2015 The C code used to detect road lanes was synthesized and the design was implemented on FPGA. FPGA implementation improved speed. This design has its use in applications such as autonomous driving

• Logic Level Dynamic Power Estimation Tool Spring 2016 Developed a Tool using Perl language to calculate dynamic power which was displayed in a GUI designed using Perl- Tk toolkit. This tool could calculate power for any complex circuit with multiple delays.

• Research on IEEE paper ‘Automatic verification of floating point units’ published in the year 2014 Spring 2015 Verified Floating point instructions in a pipeline using Model and equivalence checking. This verification was automatic and had an advantage of including both control and datapath aspects of FPUs.

• Verification of a single port RAM ( 256 x 32) Spring 2015 Verified a single port RAM using System Verilog. Control aspects of the RAM were verified using system Verilog assertions

TECHNICAL SKILLS

Programming Languages: Verilog, Perl, Python, C, C++, UVM, System Verilog Tools Used: Vivado HLS, Synopsys VCS, Formality, Cadence Virtuoso, Mentor Graphics IC studio Xilinx Vivado, Synopsys IC Compiler, DFT compiler, DC compiler, ModelSim, Questasim Proficiency: Constraint random test cases, assertions (sva ),ASIC design and verification. CERTIFICATIONS:

Udemy course certificates on Physical design, Static timing analysis . EDUCATION

Santa Clara University, Santa Clara, CA June 2016

M.S. in Electrical Engineering (VLSI Design and verification) Relevant Coursework:

VLSI design and computer networking courses

St Francis Institute of Technology, Mumbai, INDIA June 2013 B.S. in Electronics and Telecommunication

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