Sign in

Design Engineer

San Jose, California, United States
March 08, 2018

Contact this candidate

*** *********** ******, #*** ********* VISHWESHWAR NANDEDKAR

Mountain View, CA-94040 Tel: (917) ***-**** OBJECTIVE

Seeking full-time opportunities in the field of FPGA Design / ASIC Design / Design Verification / Physical Design / Embedded Design. RELEVANT WORK

Design Engineer Research Assistant New York University August 2016 - Present

• Designed a non-destructive method to detect anomalies in FPGA. The project was completed in two steps.

• Implementation:

o Implemented Python scripts and low level design VHDL scripts based on the FPGA layout, accessed with the help of Xilinx ISE simulator, using LUTs, LDCEs and Multiplexers in configurable logic blocks of different FPGAs, such as 22nm technology based Nexys 4, PYNQ and 28nm Artix 7.

o Defined three different architectures for the design, to improve reliability of the design, based on routing of designated Ring Oscillators (RO) in FPGA layout.

• Analysis:

o Extracted operating frequencies of ROs with similar logic and routing, in different environmental conditions, over a period of one month. o Developed MATLAB scripts to perform row and column correlation on the data. Variation observed without anomalies was -1.5% to 1%. o The Trojans (anomalies) were inserted in regions like LUT’s, FF’s and Carry Logic on CLBs for the testing purposes. o Abnormal variations observed with anomalies helped determine areas in which FPGAs could not be trusted. Research and Teaching Assistant New York University August 2016 – December 2016

• Delivered a range of tutorials to explain the implementation of different designs such as RC5 and Single Cycle MIPS, using Nexys 4 DDR FPGA board and VHDL language for undergraduate and Graduate students.

• Implemented various VHDL test benches for verification of the designs implemented by the students.

• Contributed to research regarding FPGA fingerprinting, which uses encrypted messages to avoid collusion of sensitive information. SRAM Design using 45nm technology New York University August 2016 – December 2016

• Developed a 64 Bit SRAM using 45nm technology and 800mv supply, on Cadence Virtuoso [NCSU 45nm library] in a team of four.

• Implemented the SRAM Cell with read margin of 25% VDD, write Margin of 35% VDD, PRE-charge circuit, Address Decoder circuit with delay of 22.25% TClk and Sense amplifier with 21mv bit differential voltage.

• Successfully achieved the target speed of 1.5 GHz and SRAM layout size less than 0.8 u. sq. m. Operational Amplifier Jan 2016 – May 2016

• Designed an Operational Amplifier using Two Stage Operational Transconductance Amplifier approach, as it gives large gain, high voltage swing and high bandwidth.

• Used Cadence Virtuoso to design transistor level model for the amplifier.

• Successfully achieved the target closed loop gain of 1.96dB and a slew rate of 35.43V/uS. MIPS CPU Design New York University January 2016 – May 2016

• Designed an RTL based single cycle 32 bit MIPS processor and implemented it using Verilog, on Nexys 4 DDR FPGA.

• Implemented 12 instructions and techniques which would enable the Simple MIPS CPU to have addressing modes such as Indexed addressing and Auto-increment and Auto-decrement modes. PageRank New York University August 2015 – December 2015

• Implemented NOC architecture based page rank system for 64 websites where 4-page Rank engines communicate with each other using two routers. The designed algorithm gave IDs of top ten websites having highest importance.

• Designed working routers, requestors and responder modules using Verilog on VSIM-MentorGraphics software and successfully synthesized the design using Cadence RC tool.

Configurable Gaming Music New York University August 2016 – December 2016

• Designed a game with the help of PyGame and Pyaudio library in Python.

• The background music was time_scaled based on the difficulty level achieved by the user while playing the game.

• Created a user interface with the help of PyGame, which provided options to select different songs and time scales. TECHNICAL SKILLS

Languages: Verilog, System Verilog, VHDL, C, Python, Perl, Assembly language,TCL. Design Tools: Cadence Virtuoso, Xilinx ISE, MODELSIM, KEIL, MATLAB, PuTTY, Altera Quartus, Multisim, Proteus, Vivado, Spice, Questasim. Hardware: VLSI, FPGA, ASIC, SOC, CMOS, RTL design, IP design, Digital design, Analog design, Simulation and synthesis, Formal verification, Static timing analysis, Place and Route, Electronic design automation(EDA), Integrated circuits, Computer architecture, Firmware, OVM, UVM. Operating Systems: X86, OS X, Windows, Linux, XV6. EDUCATION

New York University, New York, USA Fall 2015 – Spring 2017 Masters in Electrical and Computer Engineering GPA 3.3/4 Coursework: VLSI, Advanced Hardware Descriptive language, Analog Integrated Circuits, Solid State Devices, Embedded Systems. Vishwakarma Institute of Technology, Pune, India Fall 2011 – Spring 2015 Bachelor of Technology in Electronics and Telecommunication Engineering with Honors in VLSI GPA 3.6/4 Coursework: Integrated circuit design, Hardware Descriptive language, Mixed Signal VLSI Design, Data Structure and Algorithms.

Contact this candidate