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Design Engineer

San Jose, CA
March 13, 2018

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Chilati Shah

San Jose, CA +1-669-***-**** OBJECTIVE

Actively seeking Full-time opportunities in the field of ASIC/ RTL/ SoC/ FPGA/ Hardware design, Product development and Design verification. EDUCATION

MS, San Jose State University, Electrical Engineering GPA: 3.56/4 Jan 2016 – Dec 2017 Special Topics in Digital Systems(UVM), ASIC CMOS Design, SOC Design and Verification with System Verilog, Digital Design for DSP/ Communication, Advanced Computer Architectures, Digital Systems Design and Synthesis, Semiconductor Devices. B.Tech, Ganpat University, Electronics & Communication Engineering GPA: 3.60/4 Aug 2011 – May 2015 Digital Electronics, Network Analysis, Micro-processor Architecture and Programming, Digital Design using HDL, Microcontroller and interfacing, Digital Communication, Embedded Systems and Applications, Digital Signal Processing, VLSI Technology, Digital Communication TECHNICAL SKILLS

Hardware Descriptive Language : Verilog, System Verilog(SV) Verification Methodology : System Verilog Assertions(SVA), Verilog, Universal Verification Methodology (UVM) Programming Language : C, Embedded C, Python, Perl, Assembly language, TCL, Object oriented programming Bus Protocols : AMBA, AHB, APB, AXI4, AXI4-Lite, CAN, SPI, UART, I2C, Ethernet EDA Tools : Synopsys VCS, Design Compiler, Design Vision, Cadence Virtuoso, Xilinx ISE, Vivado, Altera Quartus, Other Skills : ASIC Design, RTL design, Design Synthesis, Static Timing Analysis, Place and Route, JTAG, Block level verification, DFT, BIST, CDC, SDC timing constraint, Functional Coverage, Area and Power optimization, D-algorithm, Scan Chain, Constraint Random Testing, Logical Equivalency checking, RISC-V, Chisel WORK EXPERIENCE

Hardware Design Engineer Intern, LeWiz Communication Inc, San Jose, CA June 2017-Dec 2017

• Successfully developed an application to remotely update the Flash memory on an Xilinx Zynq FPGA.

• Task included data extraction from SRecord file and generating a new file from which user application can update the flash.

• To improve user experience, developed a C code to erase the flash memory remotely which can be used prior to writing data on it.

• After this initial release, current task is to achieve the same results over ethernet as a medium for updating flash memory.

• Integrating TCP ethernet and flash write code to make an application which can perform read, write and verify data on flash. Development Engineer Intern, VLSI (I) PVT LTD, Ahmedabad, India Jan 2015 – May 2015

• Successfully completed the project on Home Automation using GSM 900 and ZigBee in a team comprising of four people.

• Modules like UART, SPI, ZigBee and GSM modules were configured using Embedded C.

• Modules was tested to determine the consumer related issues and each encountered issue was reported in the documentation. ACADEMIC PROJECTS

Functional Verification of 32-bit MIPS Processor (UVM, MARS, SV, Python)

• Created a strategy document and test bench architecture from scratch for verification of two 32-bit 5 stage MIPS Processor.

• Developed a python script that generates assembly language code for different R-type, I-type and J-type instructions.

• MARS simulator is used as a reference golden model and achieved 95% code coverage for functional coverage collection. UVM Verification of UART block of Atmel 8271 micro controller (SV, UVM)

• Developed UVM environment for UART with constraint random tests with programmable data width and baud rate.

• Designed constraint random sequences to verify different functionality of UART.

• Implemented a self-checking monitor to verify written register using read cycle.

• Designed scoreboards to calculate expected outputs of inserted sequences and cross verify with design output. Design and implementation of CAN Transmitter and AMBA APB bus (SV, VCS, Synopsys DC)

• Designed a BOSCH CAN bus transmitter using System Verilog and then added APB bus as an interface to send message to CAN.

• Implemented Parallel-Serial Interface for serial communication and implemented bit stuffing for error handling.

• Successfully synthesized the design at 250 MHz using Synopsys Design Compiler.

• The project was further extended to design and implement a AMBA AHB multi-master design having 8 bus masters.

• For multi-master purpose designed a priority-based arbitrator to decide which bus master should be granted access of the bus. Source Routing Network Switch (Verilog, VCS, Synopsys DC)

• Designed and implemented a receiver for the switch that had 32 input ports using a state machine that checks for legal packets.

• Implemented a 1-flag push model, CRC engine, FIFO as the input data was burst, and an arbiter mechanism to control input traffic.

• Successfully synthesized the design at 250 MHz using Synopsys Design Complier. Designed PID controller (Verilog, VCS, DC compiler, Place and Route, Encounter)

• Designed and Synthesized a PID controller on Synopsys design compiler that initially works on 200 MHz frequency.

• Further improved the design by pipelining technique to run the design at 300 MHz frequency.

• Floorplanning was done on Encounter place and route tool to implement the generated netlist and performed clock tree synthesis. Un-Pipelined and 5-stage Pipelined IEEE 754 Single-Precision Floating Point Adder (Verilog, SDC)

• Designed, implemented, synthesized and verified un-pipelined IEEE format single-precision floating-point adder.

• Implemented 5-stage pipeline to improve the performance obtained from un-pipelined floating-point adder.

• The analysis was done on parameters like maximum frequency, area, and power consumption.

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