| Resume alert | Resumes 41 - 50 of 454 |
RF Support Engineer
San Jose, CA
... California State University, Long Beach GPA: 3.4 Degree conferred: August 2019 SKILLS Languages: Python, C, MATLAB, VHDL/Verilog Tools: Atoll, FDTD, HFSS, CAD, Xilinx, Keil Microvision, Truepath Certifications: CCNA Routing and Switching, Cisco RF ... - 2020 Dec 10
... California State University, Long Beach GPA: 3.4 Degree conferred: August 2019 SKILLS Languages: Python, C, MATLAB, VHDL/Verilog Tools: Atoll, FDTD, HFSS, CAD, Xilinx, Keil Microvision, Truepath Certifications: CCNA Routing and Switching, Cisco RF ... - 2020 Dec 10
Python Data
Santa Clara, CA, 95054
... TECHNICAL SKILLS • Tools: MATLAB, JupyterNotebook, PyCharm Eclipse, Jira, Git, Synopsys VCS, XilinxISE, ModelSim, JMP • Programming Languages: Python, MATLAB/Octave, System Verilog, C/C++, MySQL, JavaScript, CUDA • Operating Systems: Unix, Linux, ... - 2020 Nov 18
... TECHNICAL SKILLS • Tools: MATLAB, JupyterNotebook, PyCharm Eclipse, Jira, Git, Synopsys VCS, XilinxISE, ModelSim, JMP • Programming Languages: Python, MATLAB/Octave, System Verilog, C/C++, MySQL, JavaScript, CUDA • Operating Systems: Unix, Linux, ... - 2020 Nov 18
Engineer Engineering
San Jose, CA
... SKILLS Programming Languages: C/C++, Python, Java, OpenMP, Perl, CUDA Design Languages: Verilog, System Verilog, UVM, CHISEL (Scala-based Design language) RAHUL NAYAR adhdm0@r.postjobfree.com • 608-***-**** • https://www.linkedin.com/in/rrahulnayar ... - 2020 Oct 28
... SKILLS Programming Languages: C/C++, Python, Java, OpenMP, Perl, CUDA Design Languages: Verilog, System Verilog, UVM, CHISEL (Scala-based Design language) RAHUL NAYAR adhdm0@r.postjobfree.com • 608-***-**** • https://www.linkedin.com/in/rrahulnayar ... - 2020 Oct 28
Sr. Electrical Engineer Design
Campbell, CA
... Developed code in C, C++, VHDL, and Verilog. FPGA development using ModelSIM, XILNX tools and Aldec tools. Project management experience. Author of 7 US patents. Work History and accomplishments Sr. Hardware Engineer Cadence Inc. San Jose Contract ... - 2020 Oct 23
... Developed code in C, C++, VHDL, and Verilog. FPGA development using ModelSIM, XILNX tools and Aldec tools. Project management experience. Author of 7 US patents. Work History and accomplishments Sr. Hardware Engineer Cadence Inc. San Jose Contract ... - 2020 Oct 23
Design Engineer Engineering
Los Gatos, CA
... •Delivered quality RTL codes using Verilog & synthesis tests using System Verilog for clock/power/pci-express units during final project milestone. Skills Project Management – Scheduling, resource planning, status tracking, risk mitigation, ... - 2020 Oct 06
... •Delivered quality RTL codes using Verilog & synthesis tests using System Verilog for clock/power/pci-express units during final project milestone. Skills Project Management – Scheduling, resource planning, status tracking, risk mitigation, ... - 2020 Oct 06
Embedded/Firmware Engineer
Fremont, CA, 94536
... in Computer Science and Engineering, • GPA: 3.58, Dean’s Honors List- Fall 2016, Fall 2017, Winter 2018, Spring 2019, Winter 2020, Spring 2020 RELEVANT COURSES Intro to Digital Systems (System Verilog), Programming with Software Libraries (Python), ... - 2020 Aug 28
... in Computer Science and Engineering, • GPA: 3.58, Dean’s Honors List- Fall 2016, Fall 2017, Winter 2018, Spring 2019, Winter 2020, Spring 2020 RELEVANT COURSES Intro to Digital Systems (System Verilog), Programming with Software Libraries (Python), ... - 2020 Aug 28
Design Engineering
San Jose, CA
... SKILLS: HDLs / HVLs: Verilog, SystemVerilog, JavaScript, Python Scripting, Object Oriented Programming (OOP). Methodology: UVM (Universal Verification methodology). Bus protocols: AMBA ARM AHB, APB, PCI. Simulation tools: Synopsys VCS, PrimeTime, ... - 2020 Aug 05
... SKILLS: HDLs / HVLs: Verilog, SystemVerilog, JavaScript, Python Scripting, Object Oriented Programming (OOP). Methodology: UVM (Universal Verification methodology). Bus protocols: AMBA ARM AHB, APB, PCI. Simulation tools: Synopsys VCS, PrimeTime, ... - 2020 Aug 05
Engineer
San Jose, CA, 95135
... Visual Studio, Matlab, System Verilog VHDL RTL, Matlab, Xilinx ISE, Python 2.7. Reference • Upon your request - 2020 Aug 05
... Visual Studio, Matlab, System Verilog VHDL RTL, Matlab, Xilinx ISE, Python 2.7. Reference • Upon your request - 2020 Aug 05
Engineer Electrical
San Jose, CA
... SKILLS Languages C, Python, CAPL script, Verilog, C++, microprocessor xx86 ALP Tools Vector CANalyzer, Peak, Intrepid NeoVI, TI Packet Sniffer, FMEA/HARA, Wireshark, EMI/EMC, Cadence, LabView. Lab Tool & Skills CANoe, Altium PCB, Oscilloscope, NI & ... - 2020 Jul 26
... SKILLS Languages C, Python, CAPL script, Verilog, C++, microprocessor xx86 ALP Tools Vector CANalyzer, Peak, Intrepid NeoVI, TI Packet Sniffer, FMEA/HARA, Wireshark, EMI/EMC, Cadence, LabView. Lab Tool & Skills CANoe, Altium PCB, Oscilloscope, NI & ... - 2020 Jul 26
Design Engineering
Santa Clara, CA
... TECHNICAL SKILLS Hardware Description/ Programming/Scripting Languages: VHDL, Verilog HDL, System Verilog, Raspberry Pi, Python, Perl Design Tools: Cadence (Virtuoso, Encounter), Synopsys (DC Compiler, Formality), Calibre, LabView, Xilinx ISE. ... - 2020 Jul 13
... TECHNICAL SKILLS Hardware Description/ Programming/Scripting Languages: VHDL, Verilog HDL, System Verilog, Raspberry Pi, Python, Perl Design Tools: Cadence (Virtuoso, Encounter), Synopsys (DC Compiler, Formality), Calibre, LabView, Xilinx ISE. ... - 2020 Jul 13