RAHUL NAYAR

adhdm0@r.postjobfree.com • 608-***-**** • https://www.linkedin.com/in/rrahulnayar

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EXPERIENCE

NVIDIA

ASIC ENGINEER II, HARDWARE DESIGN VERIFICATION

• Wrote tests in C++ to test GPU work scheduling subsystem, which were instrumental in catching design and architecture bugs.

• Owned, conceptualized, designed and coded the entire virtual address space implementation in testbench.

• Drove the feature from inception to completion through various phases such as microarchitectural guidance, test planning, risk mitigation and coverage closure.

• Set performance goals for the design which were validated by adding and maintaining an updating an exhaustive list of performance tests.

NVIDIA

ASIC ENGINEER, HARDWARE DESIGN VERIFICATION (FULL CHIP)

• Verified and validated GPU architecture at full-chip level.

• Validated GPU-to-GPU communications on UVM/Vera based testbench for system memory to video memory communications which were critical for validating GPU Unified Virtual Memory protocols and memory coherence features.

• Wrote test cases to validate GPU architectures avoid deadlocks in multi-GPU configuration. UNIVERSITY OF WISCONSIN-MADISON

RESEARCH ASSOCIATE, VERTICAL RESEARCH GROUP

• Coded an adaptive function streaming model using python to emulate Machine Learning workloads. These workloads were passed to High-Performance CPU designs to test and validate its performance.

UNIVERSITY OF WISCONSIN-MADISON

COURSE LECTURER, CS 252 (INTRODUCTION TO COMPUTER ENGINEERING)

• Teaching Introduction to Computer Engineering to a class of 300 students, with two TAs to help run the course. [ http://pages.cs.wisc.edu/~rrahulnayar/cs252/Spring2017/index.html ]

• Set up course structure, exams, assignments and grading the entire class. TATA CONSULTANCY SERVICES

BUSINESS INTELLIGENCE CONSULTANT, INSTRUCTOR FOR NEW HIRES IN GLOBAL LEARNING CENTER

• Worked on different data mining theories, methodologies, architecture, and technologies to transform raw data and extract performance indicators for business purposes.

• Promoted to an Instructor after training at TCS Learning Center, to teach and introduce new recruits about Business Intelligence Process Management. INTERNSHIPS

· NVIDIA (May 2017-Aug 2017):

• Setup testbench and wrote test cases for GPU work scheduling unit for QoS verification and was able to get a full time offer from this work.

· NVIDIA (Jan 2013-June 2013):

• Wrote test cases for design testing and constraint files for clock domain analysis.

• Set up testbench and generate coverage reports for SoC Verification team. Santa Clara, CA

Jun’18 – current

Bangalore, India

Jun’14 – Aug’16

Madison, WI

Aug’17 – May’18

Madison, WI

Jan`17 – Aug`17

Bangalore, India

Dec`13 – Jun`14

SUMMARY

Hardware engineer with experience in Design Verification. SKILLS

Programming Languages: C/C++, Python, Java, OpenMP, Perl, CUDA Design Languages: Verilog, System Verilog, UVM, CHISEL (Scala-based Design language) RAHUL NAYAR

adhdm0@r.postjobfree.com • 608-***-**** • https://www.linkedin.com/in/rrahulnayar Page 2 of 2

· Coded and Implemented a RISC-V based four-width Out of Order Processor in Scala:

• https://github.com/rrahulnayar/risc5_ooo

· Parallelize and Improve the performance OFDM (Orthogonal Frequency Division Multiplexer) simulator with OpenMP and Cuda:

• https://github.com/rrahulnayar/759Project

· Additional projects available in GitHub: https://github.com/rrahulnayar/ EDUCATION

UNIVERSITY OF WISCONSIN-MADISON

Master of Science, Computer Science Year of Graduation 2018 Specializations: Computer Architecture, Artificial Intelligence, High-Performance Computing, Operating Systems Compilers and Machine Learning

BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE - PILANI Bachelor of Engineering, Electrical and Electronics Engineering Year of Graduation 2013 Student Recruiting coordinator for the Electrical Department, Highest academic performer in Department. CGPA

(9.36/10 distinction).

Thesis: Bhabha Atomic Research Center (BARC) (May 2011- July 2011) Program the 8085 timer for four different acquisition methods implemented in the PIG (Pipe Inspection Gauge)

S

OPEN SOURCE PROJECTS

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