Design Engineering

HRISHIKESH PUJARI

**********.******@****.*** 669-***-**** San Jose, CA linkedin.com/in/h-pujari/ github.com/hrishikeshpujari SUMMARY:

• Looking for a full-time position as Design Verification Engineer to start from July 2020. EDUCATION:

Master of Science in Electrical Engineering (MSEE focus: Design and Verification) (Aug 2018 - May 2020) San Jose State University, San Jose, California. (GPA: 3.4/4.0).

• Related Coursework: Logic Verification with UVM, SoC Design using SystemVerilog, ASIC Design, Digital Logic Design, Advanced Computer Architecture.

Bachelor of Engineering in Electronics. (Aug 2013 - May 2017) University of Mumbai, Mumbai, India. (GPA: 3.5/4.0). SKILLS:

HDLs / HVLs: Verilog, SystemVerilog, JavaScript, Python Scripting, Object Oriented Programming (OOP). Methodology: UVM (Universal Verification methodology). Bus protocols: AMBA ARM AHB, APB, PCI.

Simulation tools: Synopsys VCS, PrimeTime, Cadence NC-Verilog, DVE waveform viewer, Xilinx Vivado, Quartus 2, Git. Relevant concepts: SystemVerilog Assertions (SVA), Functional Coverage, Constraint Random Verification. ACADEMIC PROJECTS:

Functional Verification of Flex Timer (FTM) in NXP SoC, SJSU. (SystemVerilog, UVM)

• Developed UVM based test bench environment in SystemVerilog for verification of the blocks of the Flex Timer.

• Created a Behavioral DUT Model for emulation, Test, Environments, Agent, Driver, Monitor, scoreboard & sequence.

• Generated sequences for direct testing to set registers. Inserted bugs in DUT to check correctness of testbench. SoC Verification of Bit Movement on AHB Bus Fabric, SJSU. (SystemVerilog, UVM)

• Created a UVM test bench from scratch for verifying the Bit Movement Engine on an AHB bus for 1 device scenario.

• Wrote sequences to create memory with random elements using constrained-random stimulus for BM configuration. Design Verification of Vending Machine DUT, SJSU. (SystemVerilog, UVM)

• Performed verification of FSMs by creating UVM TestBench using directed sequence stimulus, Queues, & TLM Ports.

• Built Reference Model & checkers to verify RTL using Pulse Detector & Accumulator. Discovered critical design bugs. Design of a Split-Cache Controller, SJSU. (SV, Computer Architecture)

• Designing a Split-Cache Controller for simulation with Split L1 Cache backed by a shared L2 Cache in SystemVerilog.

• Both the caches employ inclusivity and implement MESI protocol to maintain the inclusivity. ASIC Verification of an ALU, SJSU. (SystemVerilog, UVM)

• Developed message based UVM testbench driver, monitor, agent, scoreboard, environment, sequence from scratch.

• Generated 500 stimuli using constrained randomization for random testing of the operation of 32-bit ALU. SoC Design & integration of a Bit Movement (BM) Engine and AHB Fabric, SJSU. (SystemVerilog)

• The BM engine moves data from source to destination memory based on configuration received from Master Memory.

• Designed and simulated a modular SoC with Engine, FIFO & all AHB Fabric parts in synthesizable SystemVerilog.

• Led a team of 3. Integrated the BM Engine with AHB Fabric. Did Unix shell-scripting for build/run automation. RTL Design of Convolutional Neural Network (CNN), SJSU. (Verilog)

• Built a CNN in synthesizable Verilog to read and write to a 3-ported memory & to calculate output using Accumulation.

• Implemented 2 flag pipeline model to speed up the design and achieve a speed of 250MHz. Design of a FIFO with SCAN for DFT, SJSU. (Verilog, DFT)

• Designed a 32x32 entry synchronous FIFO in synthesizable Verilog with read, write, empty and full conditions.

• Did scan insertion to make a shift register, added SCAN Flip Flops to implement & enable SCAN testing of the FIFO. WORK EXPERIENCE:

Teaching Assistant, San Jose State University, San Jose, CA. (Sep 2019 - May 2020)

• Graded and helped undergraduate students understand the Digital Signal Processing concepts. Solutions Analyst, Sankey Business Solutions, Mumbai, India. (Jun 2017 - Jun 2018)

• Worked in a fast-paced start-up and developed backend software logic for a sales-based product in JavaScript. Hardware Engineering Intern, Larsen & Toubro (L&T) Heavy Engineering, Mumbai, India. (Dec 2016 - Jan 2017)

• Worked on creating a Verilog based RTL design using synthesizable Verilog for a linearly operating barrel controller.

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