Design Engineering

AKHILA KOMMIREDDY

+1-312-***-**** https://www.linkedin.com/in/kommireddy-akhila/ ***********@****.***.*** EDUCATION

• MS in Electrical and Computer Engineering – Illinois Institute of Technology, Chicago, IL May 2020 Courses: Advanced VLSI Design, Computer Organization and Design, Advanced Computer architecture, Integrated Circuits, Hardware and Software Codesign, System on Chip Design (SOC), Semiconductor Devices, Application Software Design.

• BTech in Electronics & Communication Engineering - SRM Institute of Science and Technology May 2018 Courses: Introduction to VLSI Design, Microprocessors and Microcontrollers, Electronics Device Theory, Computer Networks. TECHNICAL SKILLS

Hardware Description/ Programming/Scripting Languages: VHDL, Verilog HDL, System Verilog, Raspberry Pi, Python, Perl Design Tools: Cadence (Virtuoso, Encounter), Synopsys (DC Compiler, Formality), Calibre, LabView, Xilinx ISE. Simulation Tools: ModelSim, HSPICE, MATLAB, Pspice, Open Space 3D. Technology nodes/OS: 24nm PDK, Windows, MAC, UNIX. PROFESSIONAL EXPERIENCE

Product Design Engineering Intern - MIC Electronics Pvt. Ltd. April 2017-Aug 2017

● GSM based streetlight monitoring & control system is an automated system designed to increase the efficiency and accuracy of an industry by automatically timed controlled switching of streetlights.

● This system consists of an 89C51 microcontroller which on setting of time delays switches ON/OFF the streetlights and sends the update through a phone to the specified phone number. ACADEMIC PROJECTS

FinFET Transistor Characterization and Domino Logic Operation Spring 2019

● The operation of both p-type and n-type FinFET in different operation modes is verified and the DC Transfer Characteristics is generated using Cscope. Delay and leakage power are calculated, and the design is optimized to reduce power.

● Comparison of delay and leakage current for two different domino logic implementations of 4 input AND gate (AND4) and 4 input OR gate (OR4).

Physical Design of 16-word register file with 1 read and 1 write port Spring 2019

● Designed and optimized full custom 16 entries, 16-bit wide dynamic register (8T SRAM) using a 2x4 decoders.

● Verified using DRC, LVS: functionality verification of obtained PEX netlist. Design Analysis of 32-bit CPU with new ALU architecture in RTL Fall 2018

● Designed a 32-bit pipelined CPU is implemented with an ALU using SystemVerilog.

● Designed adders (Carry Ripple, Carry Look-ahead, Carry-skip, Carry select), performed DC synthesis, Automatic Place and Route using Cadence Encounter, post P&R simulation and Equivalent checking using Formality is performed. Design and implementation of MIPS CPU in RTL with multicycle data path Fall 2018

● Designed a non-pipelined RISC processor using VHDL with an ALU design that has all control logics.

● Each instruction is simulated in the Xilinx ISE, the functioning of the processor is tested for the given processor using test bench and the simulation results are verified.

RTL Implementation of Dynamic Branch Predictors Spring 2019

● Designed the saturating counter for 1-bit and 2-bit Branch predictor and (4,2) correlating predictor using VHDL.

● Performed the functional validation and verification using ModelSim.

● Performed power analysis, cost analysis and determined the overall miss rates for each design. ASIC design of an Accumulator using 24nm Technology PDK Fall 2018

● Designed the accumulator using Verilog.

● Performed complete ASIC design flow i.e., RTL and Gate level Netlist functionality test using ModelSim, Synthesis using DC Compiler, floor planning, APR, Clock Tree Synthesis, Static Timing Analysis, reported power consumption using Cadence Encounter.

● Performed Equivalence Check using Formality.

Classification of Vegetation in industries using Spectral Imaging Spring 2017

● Designed and developed a MATLAB algorithm that can process spectral data and classify similar looking rotten/ripe organics in FMCG industry based on its spectral reflection signature.

● SAM algorithm is used for supervised classification and using the spectrographic sensors the Hyper Spectral measurements are obtained and the Data comparison is performed for validation. PUBLICATION AND PATENTS

● “Household Guide Using Augmented Reality”, publisher IEEE, 08 November 2018.

● Patent on Classification of Vegetation in industries using Spectral Imaging (Filed Oct 26, 2018 Patent issuer and number: IN 201*********).

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