| Resume alert | Resumes 101 - 110 of 508 |
Design Engineer Manager
San Jose, CA
... Expert-level User with Layout & Verification Tools: Cadence Virtuoso GXL, Calibre DRC/LVS/PEX, Hercules, ASTRO P/R, Design Compiler, StarRC-XT, Assura. Design verification tools: Hspice, HSIM, Verilog, VCS, PrimeTime SI, StarSim, and Design Compiler ... - 2018 Nov 09
... Expert-level User with Layout & Verification Tools: Cadence Virtuoso GXL, Calibre DRC/LVS/PEX, Hercules, ASTRO P/R, Design Compiler, StarRC-XT, Assura. Design verification tools: Hspice, HSIM, Verilog, VCS, PrimeTime SI, StarSim, and Design Compiler ... - 2018 Nov 09
Management Power
San Jose, CA, 95132
... LAYOUT TOOLS Cadence XL/GXL 6.1.7, 6.1.5, 12.2 and older version Cadence IC 6.1.5 Constraint Driven Custom Design Verification tools: Calibre, Hercules, DIVA, Dracula WORKING HISTORY Nokia February – May, 2018 (short term contractor) Worked on RF 5G ... - 2018 Nov 08
... LAYOUT TOOLS Cadence XL/GXL 6.1.7, 6.1.5, 12.2 and older version Cadence IC 6.1.5 Constraint Driven Custom Design Verification tools: Calibre, Hercules, DIVA, Dracula WORKING HISTORY Nokia February – May, 2018 (short term contractor) Worked on RF 5G ... - 2018 Nov 08
Engineer Electrical Engineering
San Jose, CA
Oleg Loskutoff **** ****** **., *** ****, CA ****1 530-***-**** ac7h2k@r.postjobfree.com SKILLS Software – Python, shell scripting, PyCharm, Git, C, GNU x86 assembly, Visual Studio EDA Tools – Veloce, TBX, Cadence, Quartus, SPICE, ModelSim, Synopsis ... - 2018 Oct 25
Oleg Loskutoff **** ****** **., *** ****, CA ****1 530-***-**** ac7h2k@r.postjobfree.com SKILLS Software – Python, shell scripting, PyCharm, Git, C, GNU x86 assembly, Visual Studio EDA Tools – Veloce, TBX, Cadence, Quartus, SPICE, ModelSim, Synopsis ... - 2018 Oct 25
Manager Marketing
San Jose, CA
... effectively communicate the goals of each project/initiative including logistical preparation, relevant messaging and budgetary viability, create the execution plan/repeatable process on all developing assets and maintained regular cadence reporting ... - 2018 Sep 09
... effectively communicate the goals of each project/initiative including logistical preparation, relevant messaging and budgetary viability, create the execution plan/repeatable process on all developing assets and maintained regular cadence reporting ... - 2018 Sep 09
Sales Manager
Fremont, CA
... Cisco, Apple, Microsoft, Polycom, Juniper Networks, Broadcom, Brocade, Cadence, and many other major OEMs. I also managed multiple EMS’(electronics manufacturing service) such as Flextronics, Foxconn, Celestica, Wistron, and many others. Global ... - 2018 Sep 02
... Cisco, Apple, Microsoft, Polycom, Juniper Networks, Broadcom, Brocade, Cadence, and many other major OEMs. I also managed multiple EMS’(electronics manufacturing service) such as Flextronics, Foxconn, Celestica, Wistron, and many others. Global ... - 2018 Sep 02
IC Layout Designer
Milpitas, CA
... Verification Strong debug skills to resolve a full suite of verification for IP and Full Chip, including LVS, DRC, Latchup, Antenna, Metal Fill (Waffle), and more using Calibre from Mentor Graphics and PVS from Cadence Layout Quality Collaborate to ... - 2018 Aug 29
... Verification Strong debug skills to resolve a full suite of verification for IP and Full Chip, including LVS, DRC, Latchup, Antenna, Metal Fill (Waffle), and more using Calibre from Mentor Graphics and PVS from Cadence Layout Quality Collaborate to ... - 2018 Aug 29
Electrical Engineer Design
San Jose, CA
... Packages: Cadence Spectre, Cadence Virtuoso Schematic Composer, Cadence Virtuoso XL Editor (VXL), Cadence Layout Editor (VLE), Cadence Assura DRC/LVS/Soft-Check, Synopsys VCS, Synopsys DC, LT SPICE, Dip Trace, Synopsys Primetime, Altium Designer. ... - 2018 Aug 23
... Packages: Cadence Spectre, Cadence Virtuoso Schematic Composer, Cadence Virtuoso XL Editor (VXL), Cadence Layout Editor (VLE), Cadence Assura DRC/LVS/Soft-Check, Synopsys VCS, Synopsys DC, LT SPICE, Dip Trace, Synopsys Primetime, Altium Designer. ... - 2018 Aug 23
Engineer Machine
San Jose, CA
... Spring boot, Hibernate, Phoenix Tools: Git, Maven, AWS, Docker, Kubernetes, Kafka Machine learning Framework: Tensor flow, Keras, Scikitlearn, SparkML Web Languages: HTML, CSS, JavaScript Professional Experience Cadence Design Systems, Inc. ... - 2018 Aug 22
... Spring boot, Hibernate, Phoenix Tools: Git, Maven, AWS, Docker, Kubernetes, Kafka Machine learning Framework: Tensor flow, Keras, Scikitlearn, SparkML Web Languages: HTML, CSS, JavaScript Professional Experience Cadence Design Systems, Inc. ... - 2018 Aug 22
Engineer Design
San Jose, CA
... Cadence Design Systems, Taiwan 01/1998 – 1/2002 Senior Layout Design Customer Support Application Engineer Support TSMC PDK backend layout and verification R&D team Support UMC backend layout and verification R&D team Support VIA backend layout and ... - 2018 Aug 14
... Cadence Design Systems, Taiwan 01/1998 – 1/2002 Senior Layout Design Customer Support Application Engineer Support TSMC PDK backend layout and verification R&D team Support UMC backend layout and verification R&D team Support VIA backend layout and ... - 2018 Aug 14
System Administrator Design
Dublin, CA
... Layout Tools & Computer Skills Layout Tools: Cadence Virtuoso Layout Editor (VLE), Virtuoso XL Editor (VXL). Cadence Assura Diva DRC/LVS and Dracula DRC/LVS. Cadence Virtuoso Chip Assembly Router (VCR) Place & Route tool. Synopsys Hercules DRC/LVS ... - 2018 Aug 08
... Layout Tools & Computer Skills Layout Tools: Cadence Virtuoso Layout Editor (VLE), Virtuoso XL Editor (VXL). Cadence Assura Diva DRC/LVS and Dracula DRC/LVS. Cadence Virtuoso Chip Assembly Router (VCR) Place & Route tool. Synopsys Hercules DRC/LVS ... - 2018 Aug 08