Tiffany Tung
San Jose, Ca. *****
Cell phone: 408-***-****
ac7m24@r.postjobfree.com
OBJECTIVE
Look for a challenge layout position.
SKILL
Complete complex full custom analog and mix signal layout from floor plan, layout, verification to tape in.
Familiar analog layout techniques, such as: matching, isolation, antenna effect, ESD, latch-up and IR drop prevention, etc.
Work on different processes, such as TSMC0.13, TSMC0.25, TSMC28nm, TSMC16nm, Chartered 0.065, Dongbu0.18, Dongbu0.25, Jazz 0.18, UMC12, UMC20, SC12, SC20, Tower0.18, bipolar and so on.
Familiar 15KV high ESD I/O and latch-up prevention layout.
Develop standard and custom cell libraries.
Layout test chips for new processes.
Applies top down and bottom up approaches and techniques for floor plan and layout.
Utilize CAD tools for verifications. Run DRC, LVS, XOR, antenna and metal density to achieve the zero error goals. Use Cliosoft data management tool.
LAYOUT TOOLS
Cadence XL/GXL 6.1.7, 6.1.5, 12.2 and older version
Cadence IC 6.1.5 Constraint Driven Custom Design
Verification tools: Calibre, Hercules, DIVA, Dracula
WORKING HISTORY
Nokia February – May, 2018 (short term contractor)
Worked on RF 5G chip.
Layouted temp sensor.
Modified RX.
Maxlinear Corparation May, 2017 – September, 2017
Worked on power management chip revisions.
Estimated new project die size and scheduling.
Studied tsmc28nm design menu and helped with fixing poly density.
Studied tsmc16nm design menu and layouted a small block.
Exar Corparation August, 2007 – May, 2017
Responsible on mixed signal, digital power management, analog power management and high voltage (80v and 40v) high ESD interface chip.
Good experience on analog flow and digital flow for mixed signal projects.
Layouted circuits like Bandgap, LDO, Voltage regulator, Oscillator, Comparator, bias, Charge Pump, PLL, Vco, Buffer, AUX_VTJ_AMP, AUX_VIN, AUX_AFE, Receiver, Driver, Filter Cap, pad ring.
Provided opinions for Pcell default setup to improve productivity.
Used new tools to speed up productivity.
Used Black Box LVS to debug lvs.
Sipex Corparation July, 1996 – August, 2007
Worked on Serial transceivers, Multi-protocol, Switching Regulators, Switching Controllers, Linear LDOs, Voltage Regulators, Fiber optic chips. Supported protocols include: RS485, RS232 and RS422. Interface modes include: V.10, V.11 and V.28.
Worked on one metal or two metals bipolar chips.
Layouted test chips for new processes.
Built standard cell libraries.
Performed chip planning, placement, layout, verification (DRC, LVS, ERC, XOR, Antenna, Metal Density) and tapeout.
EDUCATION
BA degree of Management Information System San Jose State University
AA degree of Business Administration Evergreen Valley College
LANGUAGE
Bilingual English and Chinese
STATUS
US citizen