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Electrical Engineer Design

Location:
San Jose, California, United States
Posted:
August 23, 2018

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Resume:

SHILP D MEHTA

ac6sd2@r.postjobfree.com http://www.linkedin.com/in/shilpmehta +1-408-***-****

OBJECTIVE: Electrical Engineer seeking a position that will combine my experience, strong interpersonal communication abilities and creative thinking in the semiconductor industry as a IC Layout Engineer.

EDUCATION:

Silicon Drafting Institute (Advanced BiCMOS IC Mask Layout Design), San Jose, CA Jan’18 - Present

M.S in Electrical Engineering (Analog/RF VLSI), San Jose State University, CA Jan’15 - Dec’16

B.E in Electronics & Telecommunications, University of Mumbai, Mumbai, India Jun’10 - Jun’13

TECHNICAL SKILLS:

Packages: Cadence Spectre, Cadence Virtuoso Schematic Composer, Cadence Virtuoso XL Editor (VXL), Cadence Layout Editor (VLE), Cadence Assura DRC/LVS/Soft-Check, Synopsys VCS, Synopsys DC, LT SPICE, Dip Trace, Synopsys Primetime, Altium Designer.

Programming/Scripting/Design Languages: Python, Verilog.

CMOS/BiCMOS Layout Skills

Strong knowledge of Analog, RF, Digital logic fundamentals.

Experienced in Analog layout techniques such as device matching, cross-coupling, common centroid, wire shielding,

P/G rail separation, guard rings and noise reduction techniques.

Understanding of Resistance, Capacitance, Inductance and their associated parasitic.

Designed circuit blocks like latch, D Flip-Flop and Shift Register with 0.1um 5-layer metal BiCMOS nwell technology.

Knowledge of chip floor planning with a view to obtain optimal topology and minimal die size.

Strong knowledge and ability to solve DFM issues such: Antenna diodes, metal slotting, electro migration and IR drop.

WORK EXPERIENCE

Engineering Tech/Material Handler, Applied Materials July’17 - Present

Assist in installing and configuring electrical hardware such as PLC, flow meter and arc detector.

Focal for Parts Management for storage, restock, Inspection and Quality. (CFT: Engineers/Program Managers/buyers/logistics)

Instructor Student Assistant, SJSU Aug’16 - Dec’16

ISA for the courses Analog Integrated Circuits, RFIC Design, Electronic Design & Design of CMOS Digital Integrated Circuits.

Assist students with Cadence Tool and transistor level design.

Graduate Trainee Engineer, E-Circuit Solutions June’13 - Nov’14

Tested and troubleshot powers related electronic circuit boards and managed procurement of goods for manufacturing.

Worked on complex PLCC (Power Line Carrier Communication) based electronic circuits.

PROJECTS

Full Custom layout of Mixed-Signal Phase Locked Loop (Cadence VXL)

Designed layout of PLL blocks – phase detector, low-pass filter, amplifier and VCO.

Design includes matching devices and noise reduction techniques for resistors and capacitors.

Layout of a 1k SRAM (Cadence VLE)

Designed layout of row and column decoder, read write control logic, equalization circuit for the bit line and 1k RAM core.

Maintained the same pitch cell dimension for the sub-blocks.

Encompassed the 1k RAM core with double ring guard.

Design a High FoM Bluetooth LNA in 45nm technology (Cadence Virtuoso, Cadence Spectre)

Developed a low-power LNA with input matching network operating at 2.4 GHz-2.5 GHz for a Bluetooth application using 45nm.

Optimized the designed circuit and achieved an input reflection coefficient of -16.32dB, a gain of 21dB, P1db of -9.92dBm, power consumption of 2.22mW and noise figure of 3.48dB.

Design a 32-bit Array Multiplier (Synopsys Design Compiler, Primetime, ModelSim)

Developed RTL of the 32-bit array multiplier using ripple carry and carry look ahead adders.

Compiled using Synopsys VCS and synthesized the multiplier using DC compiler by inserting constraints.

Performed static timing analysis and power analysis using Primetime to detect violations.

Design an OPAMP in 180nm technology using Gm/ID methodology (Cadence Virtuoso, Cadence Spectre)

Characterized NMOS and PMOS in Cadence by plotting Trans conductance efficiency (Gm/ID) with respect to parameters such as overdrive voltage, transit frequency, ratio of drain current to width (ID/W) and gain.

Designed an operational amplifier using the plots and achieved a gain of 63dB, bandwidth of 9.7 MHz, phase margin of 57 degrees & power consumption of 297µW.

Design a CMOS Operational Trans conductance Amplifier (Cadence Virtuoso, Cadence Spectre)

Designed with a team an operational Trans conductance amplifier using 45nm for 36dB gain, 33MHz B.W & PM of 28 degrees.

Achieved power dissipation of less than 3mW and common mode rejection ratio of greater than 18dB.

EXTRA-CURRICULAR ACTIVITIES AND CERTIFICATION

Awarded education grant for academic excellence in the year 2011-2012 by Sir Dorabji Tata Trust.

Achieved the second position in National level paper presentation @NextTech held at St. Xavier’s College of Engineering for the paper titled ‘RFID’.



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