EXPERIENCE:

Microchip Technology, San Jose CA *2/2002 - Present

Principal Layout Designer

Layout task assignment and teamwork coordinator.

Experienced in BCD/CMOS/BiCMOS analog/mixed signal layout, high-speed LAN interfaces/switch, RFIC chip, device matching/placement, signal matching, shielding, LOD/WPE/EM and IR drop.

Experienced in layout floor-planning, hierarchical layout assembly, structured/standard cell planning and generation.

Operations administration and maintenance in design rules(Calibre), SKILL programs and technology files.

In charge of whole chip integration ( ADC,PLL,LDO,IO, bandgap and Analog PHY and digital P&R ) and verification.

Assist circuit designer in bonding information creation of whole chip and FIB issue

Handle multi-task project assignment and all the GDS tape out process, eJobview and FAB out ( TSMC 0.11um, 0.13um,65nm and 40nm, SMIC 65nm and Dongbu 0.11um ).

Over 10+ years of management experience, whole chip level of Calibre debugging ( ANT/DRC/ERC and LVS ), dummy metal insertion .

Cadence Design Systems, Taiwan 01/1998 – 1/2002

Senior Layout Design Customer Support Application Engineer

Support TSMC PDK backend layout and verification R&D team

Support UMC backend layout and verification R&D team

Support VIA backend layout and verification R&D team

In charge of tools of DIVA/ASSURA, Virtuoso XL Layout Editing, SKILL Language programming and IC_Craftsman(ACPD design methodology), Customer training classes

Assist customers with the adoption and deployment of Cadence IC backend products

Mentor Graphics, Taiwan 11/1995 – 12/1997 Senior Physical Layout Design Engineer

Layout leaf-cell of Memory Builder tool for SAMSUNG project

Layout leaf-cell of Memory Builder tool for TSMC 0.5um and 0.6um process

Layout leaf-cell of Memory Builder tool for Winbond 0.35um process

Also in charge of tools of GDT Layout Editor, IC station, Calibre verification

Assist customers with the adoption and deployment of Mentor IC backend product

TOOLS and COMPUTER SKILLS:

Cadence: OPUS, Virtuoso IC5/ IC6/IC7,Virtuoso XL, IC_Craftsman (P&R),DIVA/ASSURA, PVS, SKILL Language and Dracula

Mentor: GDT Led layout tools, Checkmate, IC_Station and Calibre verification (ANT/DRC/ERC and LVS)

Windows, UNIX and LINUX

Certifications and Award: MOTOROLA SPEED & QUALITY AWARD,

Cadence Virtuoso XL, DIVA (DRC/ERC/LVS), SKILL Language, ACPD Design Flow

EDUCATION:

BS EE of CHING-YUN UNIVERSITY of TAIWAN

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