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IC Layout Designer

Location:
Milpitas, California, United States
Posted:
August 29, 2018

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Resume:

IC LAYOUT DESIGN “SILICON NEVER LIES”

It’s exciting to be a part of enhancing our daily experiences through technology.

Deliver full custom layout of analog and digital IP blocks that adhere to design rules, engineer requirements and best practices. Responsible for projects from small blocks to full chip and tapeout that includes analog, mixed signal, and P&R databases. Other responsibilities have included layout reviews, developing best practices, creating testchips and standard cells. Work with cross functional teams to deliver high quality layout that meets corporate goals.

I look forward to meeting the challenges analog layout brings and develop RF skills.

CURRENT EXPERIENCE

Contract – Analog Layout Designer – Spectra7, San Jose (1/2018 – Present)

Custom Layout and verification of high speed blocks for VR chips. Rework existing blocks.

Contract – Analog Layout Designer – Seamless Devices, San Jose (8/2017 – 1/2018)

Custom layout of high speed, high performance ADC

Contract – Analog Layout Designer – Cypress Semiconductor - Ireland Design Center, remote (5/2017 – 7/2017)

Analog layout, block routing and finishing, DRC, LVS, Latchup, Antenna verification

Cypress Semiconductor – San Jose, CA (12/1987 – 12/2016)

Analog and Digital Blocks and Chips

Blocks: Power sensing, Op Amps, Level Shifters, ADC’s, I/O’s, Regulators, Flash Macros, wordline drivers, control logic, memory pitch circuitry, Sense Amps, standard cells, and more

Full Chip: Programmable Systems on Chip (PSOC’s), USB-C, USB3, USB2, USB, Touch, Cap Sense, Clocks, Image Sensors, NSE’s, full custom SRAM and QDR Memories, and Test Chips

Schematics: Modify schematics to add dummies, change fingers/m-factor for matching devices

Corporate Portfolio: Automotive, industrial, home automation and appliances, medical, and consumer electronic businesses like touch screen solutions, cap sense, finger print, MCUs, memories, analog ICs, USB controllers, IoT

Technology: CMOS technology with Dnwell in 28nm, 40nm, 65nm, 90nm, 130nm

Senior Staff Layout Designer – Created global review process to ensure better performance the first time.

Full Custom Analog Practices

Match devices using common centroid and interdigitating devices, routing to reduce capacitance, shielding, determining device fingers, adding dummies/LOD, node sharing, proper contacting, and latchup protection

Full Chip Layout Responsibilities, Chip Integration Group

Import to tapeout of multi-voltage P&R mixed signal databases, including verification, fixing complex LVS and DRC issues and feedback issues to engineers. Minimize layers used for ECO changes, saving in mask costs

Collaboration

Work with engineers for analog requirements. Member of cross-functional teams participating in CAD issues, design methodology and productivity enhancements. Written 300+ memos on procedures, reviews and tapeouts

Staff Layout Designer – Custom Analog Layout, P&R database verification and hand editing

General Layout Techniques for Analog and Digital

Creating robust layout using best practices and DFM (Design for Manufacturing), with strong power and ground grids, and with protection against latchup and antenna issues

Connectivity

Maintain connectivity for nets and devices using VXL/SDL (Schematic Driven Layout, a.k.a. Generate Source from Schematic) along with manual net and device naming

Compact Layout

Share common nodes, wells, guard rings, use good device placement to shorten line length and reduce block size. Redesign existing layout to fit new requirements.

Verification

Strong debug skills to resolve a full suite of verification for IP and Full Chip, including LVS, DRC, Latchup, Antenna, Metal Fill (Waffle), and more using Calibre from Mentor Graphics and PVS from Cadence

Layout Quality

Collaborate to set the quality bar, help teach quality and Cadence to design to a common standard and meet company expectations. Review layout and teach reviewing practices to find defects before getting to silicon, shortening design time and time to market

Layout Center of Excellence (COE) charter member: setting standards, sharing methodologies and commands, evaluating tools, documenting procedures, and teaching best practices globally

APPLICATION SKILLS

Layout using Cadence Virtuoso XL and L using IC6 and IC5. Verification suites from Mentor Graphics (Calibre) and Cadence (PVS) for DRC & LVS, latchup, antenna, soft connection, metal fill (Waffle) and more. Database management products from IC Manage/Perforce and Syncronicity. Familiar with RTL, modifying skill programs and bindkeys. Previously used Assura and Dracula

Familiar with Office Libre (Linux Word Processor) VNC, Remote Desktop, VI, Microsoft Office applications (Excel, Outlook, Word, PowerPoint, Skype), Chief Architect, video editors

Classroom understanding of FinFET and RF devices. Successfully worked in over 15 different technology nodes

PREVIOUS EXPERIENCE

ZyMos – Sunnyvale, CA - Layout Designer

National Semiconductor – Sunnyvale, CA – Digitizer, Calma Instructor

Richmar Associates – Santa Clara, CA, Printed Circuit Board Layout Designer

ADDITIONAL SKILLS

Emergency response team lead and trainer. Certified in first aid, CPR, AED through Red Cross

Volunteer Team Lead at Second Harvest Food Bank of Santa Clara County (20+ years)

Managed television broadcast studio for company meetings and CEO interviews (20+ years)

Home improvement – design, create, and manage home projects – woodworking, landscaping

Play hockey (defense) in a local league – big Sharks fan

EDUCATION

DeAnza College, Cupertino, CA - Drafting Technology, General Ed, Video Production, PCB Design, History

Online - Auditing classes in RF layout and FinFET technology



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