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Design Engineer Manager

San Jose, CA
November 09, 2018

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Hung Ngo –

Hung Ngo

San Jose, California

Objective: Seeking a Physical Design Lead or Analog/Mixed-signal Layout position where my 25+ year of circuit design with UC Berkeley EE degree will help ensure successful tight-schedule tape-outs. Circuit Design and Layout with 30+ years of Analog Layout/DRC/LVS and Physical Design: o Expert in Mixed-signal, Analog, IO and Memory circuit layout; excellent chip-level physical design. o Designed and laid out 50+ mixed-signal ICs with countless tape-outs over the years. o Fast and correct-by-construction layout due to circuit design knowledge, experience and planning. o In-depth knowledge of device electronics, analog design, Verilog, IO, digital design and verification. Lead and taped out these most recent complex and high-speed Analog Circuits: Stealth start-up in Saratoga currently leading layout effort for two complex analog IC’s. Samsung 6 years, 7 tape-outs: five SerDes UDDI, UDDI-m chips, TX Channel and Modem chip. LSI Logic 2 years: 16G ADC, 12G SerDes chips with complex analog structures in TSMC 28n. nVidia: Test-chip integration and laying out PLL, CP, FPD, VCO, FE and IO TSMC 20n. Global Foundries: High speed digital/analog circuitries in 20n IBM/Global Foundries/Samsung process. Rambus: 3-D Memory stacked chip integration, clock tree, P&R, vdd/vss/vddio TSV, RDL, flip-chip. NetLogic: PHY front-end DFE, Slicer, RX_term, Sampler, DAC in TSMC 40n. Rambus: SerDes, PreAmp, SampLat, PLL, VCO, ROs... in 28n TSMC. Cupertino start-up: IO, Data path, memory and leaf cells in 28n TSMC process. Rambus: Dsampler, Preamp, I-bias, pcas, ncas bias ckts in TSMC 0.13u. Cypress Semi: I-Sense Amp, FB_Amp, BiasGen and Buck Drivers in 60V DMOS. ZeroG Wireless: Power Amp, gm BiQuad, Bandgap, T-Sense, OTA in 0.18u RF TSMC. Atrua Technologies: chip integrations and IO cells, Memory, Datapath and ESD circuits lay out. Cray Research (Wisconsin): one-year off-site custom SRAM in 45n TSMC with VPN connection. Expert-level User with Layout & Verification Tools: Cadence Virtuoso GXL, Calibre DRC/LVS/PEX, Hercules, ASTRO P/R, Design Compiler, StarRC-XT, Assura. Design verification tools: Hspice, HSIM, Verilog, VCS, PrimeTime SI, StarSim, and Design Compiler. Back-End Physical Design Skills:

o Analog circuits: ADC, QDFE, AFE, RF power amplifier, ultra-low power gm BiQuad, OTA, FBAmp, CTLE, Temp. Sensor, PLL, VCO, Bandgap, Comparator, CP, Oscillators, V-I Clamps, 60V Current- Sense Amplifier, ESD and Biometric Capacitive Sensors. o High-speed, high density Memory, Logic and IO: 28-nano data-path circuits, 45-nano custom SRAM modules, Micro-Controllers, R/W Decode, DMA, IO cells, ESD circuits, 10ps 10-bit programmable Timing Vernier, clock distribution in 256 mm sq. chip, 65-million transistor flip-chips. o Excellent with critically matched, high-speed and highly-sensitive analog circuits, shielding, active filter, signal integrity, RAM/ROM, floor plan, IO, ESD, VDD/VSS grid, clock trees, IR, Design Compiler, Place/Route logic, IBIS, DRC/LVS, flip-chip, standard-cell, CAD set-up and run-set development. Hung Ngo – – 408-***-**** - Summary of past employers and contract clients from 1980 to present: o 2010-present: Layout at Samsung, LSI Logic, nVidia, Rambus, Global Foundries in Santa Clara, CA. o 2009: Layout at ZeroG Wireless, NetLogic Microsystems and Cypress Semiconductor in San Jose, CA. o 2003-2008: Circuit Design at three start-ups in Silicon Valley and Cray Research in Chippewa Falls, WI. o 1990-2003: Circuit Design at Credence Systems and Hitachi Microsystems in San Jose, California o 1980-1990: Circuit Design at Chips & Technologies, Micro Linear, National Semiconductor and Intersil. CMOS Layout Experience:

Samsung, San Jose, CA (Physical Design Manager – Layout Contractor) 2012 to present o Lead Physical Design, laid out analog circuits and taped out seven UDDI, UDDI-m and Modem chips. LSI Logic, San Jose, CA (Physical Design Lead – Layout Contractor) 2011-2012 o Lead Physical Design, laid out analog circuits and taped out two 12Ghz SERDES and a 16G ADC chips. nVidia, Santa Clara, CA (Physical Design Lead – Layout Contractor) 2011 o Laying out high-speed analog ckt (Charge-pump, FPD, PLL, VCO, FE and IO in 20n TSMC process. o Test chip integration, power/ground grids and full-chip drc/lvs for tape-out. RamBus in Sunnyvale, CA (Physical Design Lead – Layout Contractor) 2011 o Lead and laid out analog blocks and integrated a huge stack-chip memory device with TSV in 0.13u. o Laid out 5 GHz analog front-end (SerDes, PreAmp, SampLat, pVtBias in 28n TSMC process. Global Foundries, Sunnyvale, CA (Physical Design Lead – Layout Contractor) 2010 o Laid out complex high-speed 20/28-nano analog circuits in 40/50/100-nano grid-base CMOS process. Cupertino start-up, Cupertino, CA (Layout Contractor) 2009 o Laid out complex high-speed data path, memory and leaf cells in 28-nano TSMC CMOS process. NetLogic, Mountain View, CA (Layout Contractor) 2009 o Laid out highly complex analog blocks for a 10 GHz PHY device in 40-nano TSMC CMOS process. Debugged LVS on large blocks below top-level and cleaned up all DRC violations for tape out. Cypress Semi, San Jose, CA (Layout Contractor) 2009 o Laid out complex analog blocks for PowerSOC: Current Sense Amplifier, FB_Amp, HV Reference, Bias Generator, Current Mirrors, 30,000u Power FET Drivers, Reference Buffers and Start-Up circuit. CRAY Research, Chippewa Falls, WI (VPN offsite - Layout Contractor) 2007 o Off-site work via VPN and VNC. Laid out a custom SRAM module in TSMC 45-nano: Read Decode, Write Decode, Output Decode and Select, R/W Gated Clock Control blocks and a large 96-bit RAM slice. Hung Ngo – – 408-***-**** - ZeroG Wireless, Sunnyvale, CA (Layout Contractor) 2006 o Laid out major analog blocks on TSMC 0.18u RF device including RF Power Amplifier, gm BiQuad, Bandgap, Temp Sensor, Oscillator Timer, OTA Amplifier, R-Trim, C-Trim and various analog circuits. Atrua Technologies, Campbell, CA (Principal Circuit Design Engineer, Physical Design Lead) 2003-2008 o Laid out three finger-print sensor ASIC’s. I was in charge of chip plan, power bussing, full-chip DRC/LVS/PEX and laid out OTA, Charge Pump, Finger Detect, Over-Current Protection circuits, Sensor Array, Bandgap, Comparator, Oscillator, RAM, IO’s and ASTRO Placed/Routed the Control Logic. Credence Systems, Fremont, CA (Senior Principal Design Engineer, Physical Design Lead) 1997-2003 o Designed and laid out TSMC 0.18u 10-bit Programmable 10-ps Resolution Timing Vernier circuit. o Designed and laid out Analog Delay, Temperature Sensing circuit, Custom RAM of various sizes. o Modified IO cells from TSMC standard-IO-libraries to meet 400 MHz speed and power requirements. Hitachi Microsystems, San Jose, CA (Read Channel Manager - Principal Design Engineer) 1991-1997 o Worked on two 2u CMOS Hard-Disk-Drive Read Channel devices, laid out VCO, PLL, Bandgap, etc. o Designed and laid out PRML Viterbi Decode block, Servo Controller, Pre-Amble Detection circuits. o Was in charge of back-end and physical layout of VCO, Programmable Active Filter and AGC circuit. Chips & Tech, San Jose, CA (HDD Design Manager - Staff Design Engineer) 1989-1991 o Designed and laid out Digital Phase Lock Loop (DLL), RLL Encoder/Decoder and Servo Interface. o Developed and laid out 2u CMOS Standard Cell Library. Micro Linear, San Jose, CA (Senior Design Engineer, ADC Design) 1983-1989 o Designed and laid out most analog circuitries in seven 12-b plus sign Analog-to-Digital Converters. o Laid out two Test Chips for foundry evaluation. Developed and laid out a Standard Cell Library. National Semi, Santa Clara, CA (Design Engineer, Gate-Array Design Section Head) 3/83 to 11/83 o Designed and was in charge of physical layout for two CMOS Gate Arrays (SCX6206 and SCX6212.) Intersil, Cupertino, CA (Design Engineer, Microprocessor Group) 1980-1983 o Designed and was in charge of physical layout for a CMOS 16-bit Timer/Counter. Education: U.C. Berkeley, Electrical Engineering & Computer Science, 1980. Eta Kappa Nu. Patents & Publications: Four publications in ADC design and HDD Read Channel. US patents: 2007/0061126, 2007/0207681. Two pending US patents. LinkedIn References: 35 references attached.

Written References: Five attached references.

Verbal References: Available upon request.

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