| Resume alert | Resumes 161 - 170 of 519 |
Design Electrical Engineering
Sunnyvale, CA
... 7/4.0 Aug 2009 - July 2013 TECHNICAL SKILLS Programming languages : C, C++, Verilog, Perl, Python, System Verilog EDA Tools: Cadence Virtuoso, Cadence NCSim, Cadence SOC Encounter, Synopsys Design Compiler, Cadence Conformal LEC, Synopsys PrimeTime, ... - 2017 Oct 26
... 7/4.0 Aug 2009 - July 2013 TECHNICAL SKILLS Programming languages : C, C++, Verilog, Perl, Python, System Verilog EDA Tools: Cadence Virtuoso, Cadence NCSim, Cadence SOC Encounter, Synopsys Design Compiler, Cadence Conformal LEC, Synopsys PrimeTime, ... - 2017 Oct 26
Electrical Engineering Engineer
San Jose, CA
... (Electrical Engineering), 2016 TECHNICAL SKILLS Software Skills: C, C++, Java, MATLAB, Xilinx (VHDL), LabVIEW, MIPS, Logicworks, PSpice, Logisim, Cadence 5, Cadence 6, JDSP, Spotfire Hardware Skills: FPGA design basics, basic circuit building on ... - 2017 Oct 23
... (Electrical Engineering), 2016 TECHNICAL SKILLS Software Skills: C, C++, Java, MATLAB, Xilinx (VHDL), LabVIEW, MIPS, Logicworks, PSpice, Logisim, Cadence 5, Cadence 6, JDSP, Spotfire Hardware Skills: FPGA design basics, basic circuit building on ... - 2017 Oct 23
Project Professional Experience
San Jose, CA
... • Tools: Cadence Virtuoso, Synopsys Primetime, Atom, VCS, ModelSim, Wireshark, LabVIEW. PROFESSIONAL EXPERIENCE ASIC Verification Trainee, Verifast Technologies, San Jose, CA Sept 2016 – June 2017 • Designed a filer based self-checking verification ... - 2017 Oct 09
... • Tools: Cadence Virtuoso, Synopsys Primetime, Atom, VCS, ModelSim, Wireshark, LabVIEW. PROFESSIONAL EXPERIENCE ASIC Verification Trainee, Verifast Technologies, San Jose, CA Sept 2016 – June 2017 • Designed a filer based self-checking verification ... - 2017 Oct 09
Electrical Engineer
San Jose, CA
... language Technologies: Simulation, Debug, Functional Verification, Static timing Analysis, Logic Synthesis, Place & Route, Cadence Virtuoso Others: SPI, I2C, UART, PCAT, AXI, DFT, JTAG, SCAN, BIST, Spyder, Jupyter, IDLE, GVIM, Coverage, Assertions, ... - 2017 Oct 02
... language Technologies: Simulation, Debug, Functional Verification, Static timing Analysis, Logic Synthesis, Place & Route, Cadence Virtuoso Others: SPI, I2C, UART, PCAT, AXI, DFT, JTAG, SCAN, BIST, Spyder, Jupyter, IDLE, GVIM, Coverage, Assertions, ... - 2017 Oct 02
Sr/Staff Electrical Engineer(FPGA)
Sunnyvale, CA
... 2-year effort that involved RTL coding, test-benching, simulation, functional verification & debug using Cadence Tools. Board-level hardware bring-up using Python scripts for verifying Fpga functionality & resolving interface issues. Power-supply ... - 2017 Oct 02
... 2-year effort that involved RTL coding, test-benching, simulation, functional verification & debug using Cadence Tools. Board-level hardware bring-up using Python scripts for verifying Fpga functionality & resolving interface issues. Power-supply ... - 2017 Oct 02
Programming/ Software Development
San Jose, CA
... 3.4 COMPUTER SKILLS Programming/Languages: Python, Java, JavaScript, PHP, MySQL, HTML, MATLAB Database Management: Oracle, SQL Server Software: Microsoft Office, Cadence, Multisim Systems: Windows, Linux/Unix, Mac OS X WORK EXPERIENCE May 2016- Aug. ... - 2017 Sep 25
... 3.4 COMPUTER SKILLS Programming/Languages: Python, Java, JavaScript, PHP, MySQL, HTML, MATLAB Database Management: Oracle, SQL Server Software: Microsoft Office, Cadence, Multisim Systems: Windows, Linux/Unix, Mac OS X WORK EXPERIENCE May 2016- Aug. ... - 2017 Sep 25
ASIC Design and Verification/ Physical Design and Layout
Fremont, CA
... Design Tools: Matlab/Simulink, Xilinx ISE, Synopsys (Design Compiler), Design Vision, Altera Quartus II, ModelSim, PSPICE, Cadence Virtuoso, Cadence Encounter, Si- Soft, Oscillators, Pattern generators. Operating Systems: Unix/Linux, Windows ... - 2017 Sep 20
... Design Tools: Matlab/Simulink, Xilinx ISE, Synopsys (Design Compiler), Design Vision, Altera Quartus II, ModelSim, PSPICE, Cadence Virtuoso, Cadence Encounter, Si- Soft, Oscillators, Pattern generators. Operating Systems: Unix/Linux, Windows ... - 2017 Sep 20
Design Engineer Power
Campbell, CA
... Power circuit design experience: 15 years Simulation tool: Cadence, Mentor, Hspice. EXPERIENCE 2011 Mar ~ 2017 July: Kinetic Technology (Akros-Silicon Inc), San Jose CA As a design engineer, I’ve designed mainly PDs and Isolator. And also ... - 2017 Sep 07
... Power circuit design experience: 15 years Simulation tool: Cadence, Mentor, Hspice. EXPERIENCE 2011 Mar ~ 2017 July: Kinetic Technology (Akros-Silicon Inc), San Jose CA As a design engineer, I’ve designed mainly PDs and Isolator. And also ... - 2017 Sep 07
Junior ASIC Design Engineer
San Jose, CA, 95112
... Tools: Altera Quartus II, NIOS II, Xilinx ISE, Modelsim, Xilinx Vivado o Other Tools: Matlab, Synopsys VCS, Design Compiler, Cadence NCVerilog, MultiSim o Lab Instruments: CRO, Digital Storage Oscilloscope, Power Supply, Digital Multimeter, Function ... - 2017 Aug 30
... Tools: Altera Quartus II, NIOS II, Xilinx ISE, Modelsim, Xilinx Vivado o Other Tools: Matlab, Synopsys VCS, Design Compiler, Cadence NCVerilog, MultiSim o Lab Instruments: CRO, Digital Storage Oscilloscope, Power Supply, Digital Multimeter, Function ... - 2017 Aug 30
Electrical Engineer
San Jose, CA
... RELEVANT COURSEWORK Embedded Systems Analog Circuits Computer Architecture Microprocessor Design Fundamentals of Modern VLSI devices Digital Systems Design Digital Signal Processing Electronic Device SKILLS Cadence, P-Spice (OrCad), knowledge of ... - 2017 Aug 30
... RELEVANT COURSEWORK Embedded Systems Analog Circuits Computer Architecture Microprocessor Design Fundamentals of Modern VLSI devices Digital Systems Design Digital Signal Processing Electronic Device SKILLS Cadence, P-Spice (OrCad), knowledge of ... - 2017 Aug 30