Sr/Staff Electrical Engineer(FPGA)

Mathew Philip

*** ******** ***. *****: ***************@*****.***

Palo Alto, CA 94306 Cell-Phone: 408-***-****

OBJECTIVE

Senior/Staff EE position in Electronics Hardware Design that involves a wide range of tasks that range from FPGA design, high-speed PCB design, System-level Architecture definition, Design/Integration, and Hardware Debug/Validation.

EXPERIENCE

Reflexion Medical, Hayward, CA, USA.

FPGA Design Consultant (9-month contract) Jan/2017 – Oct/2017

Project implementing a Xilinx Zync based FPGA design interfacing to an AFE board with a series of DDC112 for very low current dosimetry measurements used on a radiation therapy system to monitor radiation dose. Tasks included system architecture, logic design with AXI4 based IP, simulation, debug, test and Hardware PCB level Analog/Digital debug, and validation on bench-top system using Xilinx SDK environment, and Vivado, ILA/Debug tools. Working with firmware team and system integration to test, calibrate, validate system-level performance on prototype system.

Violin Memory, Santa Clara, CA, USA.

Sr. FPGA Engineer (6-month contract) June/2016 – Dec/2016

Responsible for upgrading the hardware diagnostic platform used in manufacturing diagnostics test of the latest 500 MHz All-Flash Array cards. This involved upgrading an existing Altera Stratix4 FPGA based hardware platform from 250 MHz to 500 MHz using Altera Quartus II tools and debugging designs using SignalTap and Diagnostic programs, as well as debugging board related legacy and SI issues.

LitePoint Corp., Sunnyvale, CA, USA.

Sr. FPGA Engineer March/2010 – May/2016

Sr. FPGA Engineer as part of a small R&D sandbox team for developing creative solutions for existing and future Wireless Connectivity Test Instruments.

Responsibilities involve designing and implementing & testing out new experimental concepts/algorithms in FPGA that create new functionality, and solve existing System level Test problems.

Experienced in designing FPGA interfaces using DDR2 controllers, PCIe, Aurora, JESB204B, PCie DMA, DDS, High-speed serdes GTP I/O, and other Xilinx hard & soft IP cores using Xilinx Kintex-7, V6, V4, S6 devices, and Xilinx Vivado and ISE Tools.

Working in close collaboration with senior Firmware, Software, RF Systems engineers to define concept, function, specs, design trade-offs, and taking it all the way from proof-of-concept to pre-production level validation.

PCB schematic design and layout supervision of the digital baseband portion of RF PCBs. Debugging board-level hardware and FPGA design using Chipscope-Pro. Design of high-speed FPGA based board systems.

Rambus Inc., Los Altos, CA, USA.

SMTS-II (Sr Member Technical Staff) April/2006 – 0ct/2008

Senior Member of the Systems Engineering Group responsible for high-speed

PCB and FPGA design work in support of customized hardware platforms for the test and characterization of prototype Rambus test silicon IP.

This position also involved system definition, architecture and design of custom infrastructure hardware to support communication between Rambus proprietary software and the Testchip. This involved both board-level and FPGA design in collaboration with software, mechanical, chip design teams.

PCBs designed included - USB interface cards, PCIe Gen-2 PHY Serdes characterization boards, Programmable Power-supply, Power distribution, & analog/microcontroller based interface circuits – voltage, temp, current measurements, safety circuits. FPGA based Serial interfaces – USB, I2C, SPI, JTAG, and Rambus serial interface. Data-acquisition and power monitoring circuits design. FPGA design using Xilinx Virtex4 and Virtex5 devices for support of various interfaces between FPGA and Rambus PHY and Controller test hardware.

Credence Systems Corp / Schlumberger Test Systems, Milpitas, CA

Senior Hardware Engineer June/2000 – Feb/2006

ASIC verification for the mixed-signal ASIC used in the Pin Slice instruments of the Credence Sapphire Tester. 2-year effort that involved RTL coding, test-benching, simulation, functional verification & debug using Cadence Tools.

Board-level hardware bring-up using Python scripts for verifying Fpga functionality & resolving interface issues. Power-supply distribution for very high-density PCB. Switched-mode regulators, LDO, Power-integrity Analysis

Designed an cpu interface FPGA for use in an EXA3000 Pinslice board

using Xilinx Virtex2 with Synplicity & Xilinx ISE tools.

Created the schematic in ConceptHDL and supervised the Allegro layout of a

large 20-layer high-speed Sequence Control Module board as part of the development of the new DeFT structural Tester. This effort included full responsibility for design, component selection, board stack-up, documentation,

board-level STA, signal-integrity issues, and board-level debug.

Schlumberger Automated Systems, Columbus, OH, USA

Electrical Engineer IV June/1996 – June/2000

Designed a complete high-speed serial LVDS I/O Link that resulted in a major reduction in the weight of the wire-harness for discrete IO thru the flex power-track of BLU300e (Robotic Burn-in Test Handling system), thereby enabling increased performance/speed/through-put of the X-Y axis.

This design involved 4 PCBs (2 sets of mother and daughter card) connected by a twin twisted pair CAT5 flex-cable driven by LVDS transceivers at 400Mbps.

The project involved full responsibility for schematic generation, & PCB layout using PADS tools, CPLD coding & design using Altera MAXPLUSII tools, BOM generation, pcb vendor selection, Board-level debug, Bench test-fixture design, EMC testing for CE compliance at an offsite location, and ECO release.

General design & upgrade of electrical control systems related to high-speed motion-control Pick & Place robotics used in the back-end semiconductor industry.

This involved wiring-harness drawings using AutoCAD, PID Controllers, control logic modifications, servo-system sizing & design, relay-logic design, sensor & IO selection, end-of-life issues, and ECO & documentation releases.

EDUCATION

Lawrence Technological University, Southfield, MI, USA.

B.S. in Electrical Engineering, 1991 – 1995

Overall GPA: 3.15/4.0

SKILLS

Languages: Verilog, Python, Blueprint RDL, Assembly, C.

Tools: Xilinx ISE, Xilinx Vivado, Xilinx SDK, Chipscope, ModelSim, NCVerilog, ConceptHDL, Allegro PCB Viewer, Protel, BluePrint, Taray, Mentor PAD tools.

Altera Quartus, SignalTap,

Lab Equipment: Tektronix Oscilloscopes, Logic analyzers, Bert, Spectrum analyzers, Litepoint IQ-2010, IQ2200 Series Testers

Operating Systems/software: Windows10, Windows7 Unix, Linux, Microsoft office, Visio, Frame-maker, CVS, SVN, Git.

PERSONAL

Willing to accept positions that require some domestic & international travel.

Strong communication skills: bi-lingual (Fluent in English and Malay)

US citizen.

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