Electrical Engineer

Hitesh Nagpal

San Jose, CA / 669-***-**** / ******.**********@*****.*** / https://www.linkedin.com/in/hitesh-nagpal

SUMMARY

7+ months of industry experience as Hardware Engineering Intern; used Verilog (Model/Questa Sim), Python(Spyder), UVM

Completed 9+ projects utilizing Verilog, SystemVerilog, Virtuoso, VCS, NC-Verilog, Quartus Prime, ModelSim

3.855 GPA, concentration in ASIC / Digital System/Logic/CMOS-IC / SoC Design / Verification

EDUCATION

San Jose State University (M.S., Electrical Engineering) Expected 12/2017

Mahatma Gandhi Institute of Technology (JNTU-H) (B.Tech., Electronics & Communication Engineering) 5/2014

Technical Skills: Verilog, SystemVerilog, Python, UVM, VHDL, Matlab, Perl, C, Linux, Assembly language

Technologies: Simulation, Debug, Functional Verification, Static timing Analysis, Logic Synthesis, Place & Route, Cadence Virtuoso

Others: SPI, I2C, UART, PCAT, AXI, DFT, JTAG, SCAN, BIST, Spyder, Jupyter, IDLE, GVIM, Coverage, Assertions, HDMI, DP

WORK EXPERIENCE

Circuit Verification Intern (Analog Bits, Sunnyvale, CA) 06/2017 – Present

Verilog models for PVT Sensor, SCAN, PLL, XTAL oscillator, SSCG, using Model/Questa Sim; & Emulation, CTL model

PLL & Sensor IP PVT characterization, power, HTOL, using Python automation scripting; & Stub/Power Aware, UPF model

Hardware Test Engineering Intern (Granite River Labs, Santa Clara, CA) 02/2017 – 05/2017

USB2.0/3.0 SS, HS, FS, LS, interop, PET, CV, Link-layer Electrical Compliance testing, using e/xHCI, MSO, DSA, DMM

Functional (Pre)-Certification testing of Thunderbolt3.0, on Mac & Windows, involving PCIe, Ethernet, SSD, daisy-chaining

Instructional Student Assistant (Department of Aviation & Technology, San Jose State University) 02/2017 – 05/2017

Assist Professor, in "Digital Circuits" course, with grading exams, homework, & labs of 100+ undergrads, involving VHDL

Transaction Risk Investigator (Amazon.com, Hyderabad, India) 7/2014 – 12/2015

ACADEMIC EXPERIENCE

AMBA AHB, APB master/slave buses & CAN (Controller Area Network) Data Transmitter (SystemVerilog, VCS) 04/2017

Designed varying frames, CRC, bit stuffing, and bit timing to facilitate serial message transfer, viz., APB

Designed AHB’s slave mode (APB) and master mode; Designed Multi-Master AHB using arbiter, mux, decoder

Sequential & Array Binary Multipliers with Conditional Sum Adders (Verilog, VCS, Design Vision, NC-Verilog) 5/2016

Implemented RTL design & performed functional & timing verifications for synthesis; analyzed total time delay, power

Developed parametrized (Generic) code for sequential multiplier; analyzed number of clock cycles, clock period, area

32-ports bi-directional Source-routed Network Switch (Team-of-2 Project) (Verilog, VCS) 12/2016

Developed input port module using state machine & instantiated it 32 times using generate statement

Implemented FIFOs, CRC, along with arbiter & ingress scheduler to control input traffic to memory

Controlled memory interfacing & allocation with respect to FIFOs’ & memory’s statuses

Latency Measurement of Source-routed Network Switch, using UVM (Team-of-2 Master-Project) Ongoing

Measuring above design’s average packet-switching latency, using Universal Verification Methodology

Designed DUT and Stimuli (sequence) wrappers; creating UVM environment, messages, classes, monitors, scoreboard

Parameterized LMS 128-tap Adaptive FIR filters using MAC(Altera MegaWizard) (Verilog, QuartusPrime, ModelSim) 10/2016

Used IP libraries to implement RAM, multiplier, & adder blocks; implemented circular buffer in RAM blocks

Implemented parsing, rounding & saturation logic, for DSP signals; Increased performance by running 4/16 MACs in parallel

Improved Adaptive FIR filter performance by executing both FIR and LMS operations parallelly

FIR filter Hardware Accelerator, using Cyclone-V DE0-Nano-SOC board (Verilog, Quartus Prime, C) 11/2016

Built & generated system using Qsys; compiled to burn file on board

Programmed system by creating workspace using “Nios-II software build tools for Eclipse”

Designed FF, XOR, BUF with Virtuoso Schematic; ADE Test, Virtuoso Layout; Assura for DRC and LVS; Allegro 03/2017

ACTIVITIES

Demonstrated technical writing skills by writing 2800 & 7200 words’ ‘A-grade’ papers 11/2016

Organized paper-presentation event in “Microcosm,” a national level technical symposium of MGIT 03/2013

Stood in Top-10 in presenting a seminar, in a team of two, on “Tongue Drive System,” at “Microcosm” 03/2012

Used Place & Route (PNR) tool (Encounter), to create floorplan, analyze timing reports, & optimize design 10/2016

Implemented pipelining & module-interfacing to enhance a PID controller design for 200MHz & 300MHz 10/2016

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