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Junior ASIC Design Engineer

San Jose, California, 95112, United States
August 30, 2017

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Kiratey Shrikant Patil

San Jose, California

+* (408) *** ****


o Master of Science: Electrical Engineering, San Jose State University, San Jose, CA - May 2017

o Bachelor of Engineering: Electronics and Telecommunication Engineering, University of Pune, India - May 2014

o Associates in Engineering: Electronics and Telecommunication Engineering, MSBTE, Mumbai, India - May 2011

Work Experience:

o Junior ASIC Design Engineer at Scalable Systems Research Labs Inc., San Bruno, CA - July 2017 ā€“ Present

- Working in a team to design a floating-point coprocessor.

- Implementing Carry Propagate Adder and Design Verification of Alignment Shifter and other coprocessor blocks.

Technical Background:

o Skills: ASIC RTL Design, Digital Logic Design, Test-Bench Development, Assertions, Simulation, Synthesis, Static Timing Analysis, Computer Architecture, Debug, Functional and Code Coverage

o Languages: Verilog HDL, System Verilog, UVM, C, Embedded C, Assembly Language, Perl, Shell Scripting

o FPGA Tools: Altera Quartus II, NIOS II, Xilinx ISE, Modelsim, Xilinx Vivado

o Other Tools: Matlab, Synopsys VCS, Design Compiler, Cadence NCVerilog, MultiSim

o Lab Instruments: CRO, Digital Storage Oscilloscope, Power Supply, Digital Multimeter, Function Generator

o OS: UNIX, Windows, Mac


o UVM Based Verification of LCD Controller: (UVM) - May 2017

- Verification environment was built for the functional verification of LCD Controller present in the NXP 24XX using UVM.

- Multiple LCD Controller designs were verified and the code coverage for one design was obtained as high as 99.5%.

- The number of errors for each design for the particular test was noted and overall code coverage (Line and FSM coverage) were also recorded.

o Verification of CRC block on NXP MKW2xD MCU: (UVM) March 2017

- A total of 64 different test sequences designed to test all possible configurations.

- 100% functional coverage was achieved by running all tests sequentially using Synopsys VCS Urg tool.

o Design of Bidding Arbiter: (System Verilog) - Dec 2016

- Designed a Bidding Arbiter with 4 Masters and 4 Slaves.

- Master with the highest bid will get the control of the bus and if the bidding amount is same, then the control will be given based on round-robin method.

o Design of Network on a Chip and CRC Block: (System Verilog) - Oct 2016

- Designed a NoC which is a pair of a low count unidirectional (9-bit) bus acting as Bus Master as well as slave.

- Designed a CRC Block with 16/32 bit CRC Code for error detection.

o Implementing Box-Muller Transform using Random Number Distribution: (Verilog) - May 2016

- Implemented a pipelined Box-Muller transform with the data-push signal.

- Optimised the code to 220MHz.

- Implemented various modules using look-up table and worked with floating point numbers.

o Implementation of Subset of NIOS-II Instruction Set Architecture: (Verilog) - May 2016

- Designed a 5-staged pipelined RISC architecture using Altera Quartus-II and ModelSim.

- Verified the architecture with a benchmark program of Dot-product written in Assembly Language.

- Ref.:

o American Sign Language Detection: (Embedded C) - May 2014

- Designed an entire system including a sensor glove which captures the gestures made by the user.

- Ref.:

Related Coursework: Semiconductor Devices, Digital System Design and Synthesis, ASIC CMOS Design, Computer Organization and Architecture, Digital Design for DSP/Communications, SoC Design/Verification with SV, Digital System Verification, Data Structures using C, VLSI Design and Technology, Computer Networks, Micro-electromechanical Systems and SOC, Electronic Components and Applications, Programming in ā€˜Cā€™, Digital Techniques and Microprocessors.

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