Design Electrical Engineering

PRADEEPKUMAR UPADHYA KUMBHASHI

**** ***** ****** *********, ** 323-***-**** ********@***.*** www.linkedin.com/in/pradeepkumar-upadhya EDUCATION

University of Southern California, Master of Science, Electrical Engineering GPA-3.34/4.0 Aug 2015 - May 2017 Visvesvaraya Technological University, Bachelor of Engineering, Electrical Engineering GPA-3.7/4.0 Aug 2009 - July 2013 TECHNICAL SKILLS

Programming languages : C, C++, Verilog, Perl, Python, System Verilog EDA Tools: Cadence Virtuoso, Cadence NCSim, Cadence SOC Encounter, Synopsys Design Compiler, Cadence Conformal LEC, Synopsys PrimeTime, Synopsys Tetramax ATPG, Modelsim, Questasim, HSPICE Verification Methodology: UVM OS : Windows, UNIX

COURSEWORK

CMOS VLSI Circuit Design(EE477) VLSI System Design I (EE577A) Computer System Organization(EE457) Computer System Architecture(EE557) System Verification(EE599) VLSI System Design II (EE577B) WORK EXPERIENCE

ASIC Design Intern, Scalable Systems Research Labs Inc – Sunnyvale, USA Aug 2017 - Present

Working on DDR3 Memory Controller design and Verification involving initialization, processing logic and I/O FIFO Product Developer, Robert Bosch Engineering and Business Solutions– Bangalore, India Feb 2014 - July 2015

Tested and integrated automobile software as part of customer team that handled Fiat Chrysler Automobile projects

Testing involved finding design bugs in C, carrying out functionality checks and Automation of testing using Perl Project Intern, Indian Space Research Organization – Bangalore, India Jan 2013 - April 2013

Implemented Phase Locked Loop(PLL) with Phase detector and Low pass filter in Verilog, carried out Synthesis, P&R, mapped it onto Microsemi ProASIC3 FPGA and simulated the design after interfacing it with VCO ACADEMIC PROJECTS

RTL to GDSII of DDR3 DRAM Memory Controller in Verilog

Semi-custom design of DDR3 DRAM Controller involved implementation of Scalar, Block, Atomic Read and Write operations, design synthesis, logical equivalence, Static Timing Analysis and Automatic Place and Route Verification of Traffic Light Controller using UVM

Designed a class for sequences to be input on a sequencer, sent them to driver and designed a driver class to drive these sequences to DUT via virtual interface while a monitor class samples both input and output of DUT

Developed scoreboard to compare the contents with reference model and carried out coverage analysis Full Custom Design of General Purpose Multicycle Microprocessor

Designed schematic and layout of 5 stage pipelined processor with 1K BIT Single ported SRAM array as memory

Supported instruction such as AND, OR, ADD, MUL, Load, Store instructions and carried out functionality test in Perl

Involved Dynamic logic implementation, timing, power optimization and made design work at 6ns Verification of various design files in System Verilog

Verification of Asynchronous FIFO, Adder, simple FSM design by using System Verilog Assertions(SVA), Direct Randomization and carrying out simple Coverage analysis Design of 1K BIT 6-T SRAM Cell array and its Functional Test in Perl

Designed Schematic and Layout of 1K BIT SRAM cell and tested its functionality by writing a Perl program

Involved design of Row-decoder, Column-decoder, Sense Amplifier and implemented burst operation as well FPGA Prototyping using Altera DE2-115 Cyclone IV FPGA

Debugged a given Verilog code using Quartus II Web Edition Software and Altera DE2-115 Cyclone IV FPGA

Involved identifying incorrect coding, unnecessary state transitions and incorrect states in the design file Directed Research Experience Sept 2016 - Dec 2016

Design of a single Master-Slave simple AMBA AHB-Lite Protocol and Verification in UVM

Design supported operations like wrap, incremental burst of different sizes, waited transfer and error state

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