| Resume alert | Resumes 131 - 140 of 510 |
Electrical Engineering,Analog & Digital Design,Hardware Design enginee
Mountain View, CA
... SKILLS: 3 4 Hardware Description Language: Verilog 3 4 Scripting/ Programming Languages: TCL, C(basic), Unix(basic) 3 4 Simulation Tools: Modelsim, Xilinx ISE, MATLAB, Cadence, LTspice. 3 4 Tools/Packages: Synopsys 3 4 Platform: Windows, MacOS 3 4 ... - 2018 Feb 14
... SKILLS: 3 4 Hardware Description Language: Verilog 3 4 Scripting/ Programming Languages: TCL, C(basic), Unix(basic) 3 4 Simulation Tools: Modelsim, Xilinx ISE, MATLAB, Cadence, LTspice. 3 4 Tools/Packages: Synopsys 3 4 Platform: Windows, MacOS 3 4 ... - 2018 Feb 14
Analog IC Design Engineer
Fremont, CA
... The design was implemented in CADENCE and the performance was analyzed using the Cadence ADE environment. Simulations were performed with 1GSPS clock and 125 MHz input. From the FFT of the 8-bit output the SFDR achieved is 52.53dB and the figure of ... - 2018 Feb 08
... The design was implemented in CADENCE and the performance was analyzed using the Cadence ADE environment. Simulations were performed with 1GSPS clock and 125 MHz input. From the FFT of the 8-bit output the SFDR achieved is 52.53dB and the figure of ... - 2018 Feb 08
Electrical Engineer Engineering
San Jose, CA
... EDA Tools: Cadence Virtuoso, Synopsys VCS, Synopsys Design Compiler, Altium Designer 17, AutoCAD, Xilinx Vivado, Xilinx ISE. Hardware Descriptive Languages: Verilog HDL, System Verilog. Others: RTL Design using Verilog, Debug, Power Supply, Logic ... - 2018 Feb 06
... EDA Tools: Cadence Virtuoso, Synopsys VCS, Synopsys Design Compiler, Altium Designer 17, AutoCAD, Xilinx Vivado, Xilinx ISE. Hardware Descriptive Languages: Verilog HDL, System Verilog. Others: RTL Design using Verilog, Debug, Power Supply, Logic ... - 2018 Feb 06
Customer Service Technician
San Jose, CA
... Basic used of layout software Cadence, Autocad, Allegro pcb viewer Work Experience 2016 to present – Assembly/Test Technician - Intersil Corporation/Renesas. Working as a Contractor Support Engineer groups on Testing Customer Samples, Reliability, ... - 2018 Jan 30
... Basic used of layout software Cadence, Autocad, Allegro pcb viewer Work Experience 2016 to present – Assembly/Test Technician - Intersil Corporation/Renesas. Working as a Contractor Support Engineer groups on Testing Customer Samples, Reliability, ... - 2018 Jan 30
Project Service
Saratoga, CA
... Work Experience Peregrine Semiconductor(working on 110nm technology) (Nov 2015 - Sept 2017) ● Knowledge of layout of analog and digital circuits ● Expert in Cadence tools (Virtuoso, layout XL, Assura) ● Expert in LVS/DRC on hierarchical Level. ... - 2018 Jan 29
... Work Experience Peregrine Semiconductor(working on 110nm technology) (Nov 2015 - Sept 2017) ● Knowledge of layout of analog and digital circuits ● Expert in Cadence tools (Virtuoso, layout XL, Assura) ● Expert in LVS/DRC on hierarchical Level. ... - 2018 Jan 29
Engineer Professional Experience
San Jose, CA
SUGANDHA SHARMA ac35o0@r.postjobfree.com San Jose, CA 95134 352-***-**** Summary of Skills • Hands on experience with EDA tools Cadence Virtuoso (Schematic and Layout) • Proficient in analog circuit simulators Spectre and SPICE • Experience in ... - 2018 Jan 23
SUGANDHA SHARMA ac35o0@r.postjobfree.com San Jose, CA 95134 352-***-**** Summary of Skills • Hands on experience with EDA tools Cadence Virtuoso (Schematic and Layout) • Proficient in analog circuit simulators Spectre and SPICE • Experience in ... - 2018 Jan 23
Design Engineering
San Jose, CA, 95131
... Cadence Allegro, Orcad and Agile used for designs. FormFactor, Inc. Feb. 2007-June 2011 Sr. Loadboard Designer/Contractor •Designing load boards - production style. Half responsible for moving jobs around internally and offshore (Japan, India & ... - 2018 Jan 23
... Cadence Allegro, Orcad and Agile used for designs. FormFactor, Inc. Feb. 2007-June 2011 Sr. Loadboard Designer/Contractor •Designing load boards - production style. Half responsible for moving jobs around internally and offshore (Japan, India & ... - 2018 Jan 23
RF Engineer
Union City, CA
... Solar Controller, DTMF, Voice IC Technical Skills Programming Languages: C, C++,Python(beginner) Software: MATLAB, Arduino IDE, Cadence Virtuoso, Multisim, Atmel Studio, LaBView RF Equipment - Signal generator, Oscilloscope, PLC, Spectrum Analyzer, ... - 2018 Jan 15
... Solar Controller, DTMF, Voice IC Technical Skills Programming Languages: C, C++,Python(beginner) Software: MATLAB, Arduino IDE, Cadence Virtuoso, Multisim, Atmel Studio, LaBView RF Equipment - Signal generator, Oscilloscope, PLC, Spectrum Analyzer, ... - 2018 Jan 15
Verilog, Perl, Digital IC design, FPGA/ASIC design, Physical Design
San Jose, CA
... Xilinx ISE, MATLAB • EDA Tools: Synopsys – HSpice, PrimeTime, Design Compiler, IC compiler, VCS, Custom Compiler, ESP-CV Cadence – Virtuoso Schematic and Layout editor, Encounter, Conformal, Innovus Mentor – Modelsim, Calibre • Operating System: ... - 2018 Jan 11
... Xilinx ISE, MATLAB • EDA Tools: Synopsys – HSpice, PrimeTime, Design Compiler, IC compiler, VCS, Custom Compiler, ESP-CV Cadence – Virtuoso Schematic and Layout editor, Encounter, Conformal, Innovus Mentor – Modelsim, Calibre • Operating System: ... - 2018 Jan 11
Verilog, System Verilog, SV Assertions, Physical Design, DFT
Campbell, CA
... SKILLS • Programming Languages : Proficiency Level Verilog, C : System Verilog, System Verilog Assertions: VHDL, PERL : Linux Shell Scripting, X86 Assembly : • Verification Methodologies: UVM • Design Tools: Cadence Virtuoso, Cadence NC Launch, ... - 2018 Jan 07
... SKILLS • Programming Languages : Proficiency Level Verilog, C : System Verilog, System Verilog Assertions: VHDL, PERL : Linux Shell Scripting, X86 Assembly : • Verification Methodologies: UVM • Design Tools: Cadence Virtuoso, Cadence NC Launch, ... - 2018 Jan 07