Aboli Bal
*****.******@*****.*** (USA- Green Card holder- No need of visa sponsorship)
CAREER OBJECTIVE
To make use of my knowledge in the field of IC layout in Analog or Digital Work Experience Peregrine Semiconductor(working on 110nm technology)
(Nov 2015 - Sept 2017)
● Knowledge of layout of analog and digital circuits
● Expert in Cadence tools (Virtuoso, layout XL, Assura)
● Expert in LVS/DRC on hierarchical Level.
● Worked on Cell level, Block level and top level
EDUCATION
SILICON DRAFTING INSTITUTE, San Jose, California ( Aug 2012 – June 2013) Certificate course in Advanced CMOS/BICMOS
● Final Project: A BICMOS Mixed-Signal Transceiver Circuit. (0.1um) 5-layer metal Mask Layout Skills
● Strong Foundation of Transistor, Schematic, logic and complex logic functions.
● Clear understanding of IC Fabrication Steps and cross sectional view.
● Understanding of Resistance/Capacitance and associated R/C parasitics.
● Techniques used to reduce IR drop and Antenna Issues.
● Understanding of Inductance and associated L parasitic. Techniques used to reduce EM.
● Applying device matching/noise reduction techniques in Analog Circuit Layouts. Hands-On Layout Experience:
● All basic & complex logics, Data Latch, D Flip-Flop, Shift Register, Sram, PLL, Bias, Analog blocks, Digital blocks
● Clock Generator, ESD’s, I/O Devices, and Bond pads.
● Final Project: A BICMOS Mixed-Signal Transceiver Circuit. (0.1um) Layout tools:
● Cadence Virtuoso Layout Editor (VLE), Cadence VXL,
● PCELL utility, Cadence Assura DRC/LVS/Soft-Check
● Layout Tools: Dracula DRC/LVS. Cadence Chip Assembly Router (CCAR, a routing tool). UNIVERSITY OF NAGPUR, INDIA, MASTERS IN COMPUTER MANAGEMENT ( July 2006- July 2008) EXPERIENCE
Service Delivery Executive : Caliber point, India ( 11/07/2008 – 11/07/2009) M anaged data-base for Health Insurance Companies. Operating System: W indows, Linux
Programming Languages : C, VB,HTML, Knowledge of SQL queries, Tools : MS Word, Excel, PowerPoint