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Resume alert |
Resumes 111 - 120 of 512 |
San Jose, CA
... Packages: Cadence Spectre, Cadence Virtuoso Schematic Composer, Cadence Virtuoso XL Editor (VXL), Cadence Layout Editor (VLE), Cadence Assura DRC/LVS/Soft-Check, Synopsys VCS, Synopsys DC, LT SPICE, Dip Trace, Synopsys Primetime, Altium Designer. ...
- 2018 Aug 23
San Jose, CA
... Spring boot, Hibernate, Phoenix Tools: Git, Maven, AWS, Docker, Kubernetes, Kafka Machine learning Framework: Tensor flow, Keras, Scikitlearn, SparkML Web Languages: HTML, CSS, JavaScript Professional Experience Cadence Design Systems, Inc. ...
- 2018 Aug 22
San Jose, CA
... Cadence Design Systems, Taiwan 01/1998 – 1/2002 Senior Layout Design Customer Support Application Engineer Support TSMC PDK backend layout and verification R&D team Support UMC backend layout and verification R&D team Support VIA backend layout and ...
- 2018 Aug 14
Dublin, CA
... Layout Tools & Computer Skills Layout Tools: Cadence Virtuoso Layout Editor (VLE), Virtuoso XL Editor (VXL). Cadence Assura Diva DRC/LVS and Dracula DRC/LVS. Cadence Virtuoso Chip Assembly Router (VCR) Place & Route tool. Synopsys Hercules DRC/LVS ...
- 2018 Aug 08
Fremont, CA
... Universal Verification Methodology (UVM), Perl Tools: Microsoft Office, MATLAB, Xilinx ISE, Xilinx Vivado, Questa 10.0b, Cadence Virtuoso, PSpice, Synopsys VCS Operating Systems: Windows, Linux ACADEMIC PROJECTS SDRAM Controller Design A SDRAM ...
- 2018 Aug 02
San Jose, CA
... Cadence palladium Emulation platform for design software and hardware validation for live stimulus and functional coverage Developed and Debugged the various components in Constrained Driven Random Verification Environment including Generating the ...
- 2018 Jul 12
Mountain View, CA
... Has the certificate of the Cadence First and SOC Encounter. Using Laker tool generate the sub block automatically, and its DRC and LVS. Physical design, LVS, DRC and RC extraction and verification. Cadence Tools; Opus, edge, Hspice and Assura, ...
- 2018 Jun 27
Campbell, CA
... SKILL AREAS: TCL, Perl, Shell, Verilog, VHDL, Skill, ocean, Lisp, awk, sed, grep, C, Assembly 88/86/68, Python TOOLS USED: Synopsys, Cadence, Mentor, Agilent/Keysight, Silicon Frontline, Design Sync, Clio Soft, Nassda, Verilog,bda SYSTEMS USED: Sles ...
- 2018 Jun 20
San Jose, CA
... Simulation Tools: Cadence OrCAD Capture, Allegro, Xilinx Vivado, SOC Encounter, Matlab. Hardware Kit: Basys3 Artix 7 FPGA Board. Operating systems: Unix/Linux, windows family of operating systems Experience Summary: • Recently graduated electrical ...
- 2018 May 24
San Jose, CA
... C, Python, Perl, Verilog, System Verilog, UVM Tools : Xilinx Vivado, ModelSim, Synopsys VCS, Design Vision, NC-Verilog, Cadence Encounter, Design Compiler, GTK Wave, Oscilloscopes Others : Object Oriented Programming, Assertions, Cover groups, ...
- 2018 May 20