| Resume alert | Resumes 161 - 170 of 450 |
Design Engineer Electrical Engineering
San Jose, CA
... 1.9+ years of experience in System Verilog, Verilog, VHDL, Synthesis, FPGA, STA (Static Timing Analysis), DTA, C, OOPS, Unix, BIST, SCAN, DFT, Validation/Verification. 6 months of exp. In UVM Architecture specifically in Constrained Random ... - 2017 Apr 08
... 1.9+ years of experience in System Verilog, Verilog, VHDL, Synthesis, FPGA, STA (Static Timing Analysis), DTA, C, OOPS, Unix, BIST, SCAN, DFT, Validation/Verification. 6 months of exp. In UVM Architecture specifically in Constrained Random ... - 2017 Apr 08
Engineer, Design, hardware, software, teaching, Linux, Scripting
Santa Clara, CA
... Standard cell design and support for varied operating corners: Layout-view (GDSII), Schematic-view, Abstract-view generator, power-grid library, timing lookup table, timing constraints, fan-out limit, technology and cell LEF, stubs module Verilog. ... - 2017 Mar 26
... Standard cell design and support for varied operating corners: Layout-view (GDSII), Schematic-view, Abstract-view generator, power-grid library, timing lookup table, timing constraints, fan-out limit, technology and cell LEF, stubs module Verilog. ... - 2017 Mar 26
Analog/Mixed Signal IC Design
San Jose, CA
... 2009 Skills: Electronic Measurement: oscilloscope, probe station Design and Simulation Tools: Cadence Virtuoso, HSPICE, CPPsim, LTspice, EasyEDA, Eagle, Modelsim Software design and analysis: MATLAB, C/C++, Verilog, VHDL, Visual Basic, Office ... - 2017 Mar 17
... 2009 Skills: Electronic Measurement: oscilloscope, probe station Design and Simulation Tools: Cadence Virtuoso, HSPICE, CPPsim, LTspice, EasyEDA, Eagle, Modelsim Software design and analysis: MATLAB, C/C++, Verilog, VHDL, Visual Basic, Office ... - 2017 Mar 17
Engineer Design
San Jose, CA
... PROFESSIONAL SKILLS System verilog RTL programming in wide variety of projects Working knowledge of Xilinx and Altera FPGA design methodologies Working knowledge of PCIe/eMMC/SATA/SCSI and DDR2/GDDR LPDDR3/4 protocols Working knowledge of low power ... - 2017 Mar 16
... PROFESSIONAL SKILLS System verilog RTL programming in wide variety of projects Working knowledge of Xilinx and Altera FPGA design methodologies Working knowledge of PCIe/eMMC/SATA/SCSI and DDR2/GDDR LPDDR3/4 protocols Working knowledge of low power ... - 2017 Mar 16
Engineer Electrical
San Jose, CA
... QUALIFICATIONS: Specializations including verification, developing test bench using System-Verilog OVM/UVM, reusable bench environment for sub system and full chip level. Developing test plans, writing and running test using constrained random ... - 2017 Mar 15
... QUALIFICATIONS: Specializations including verification, developing test bench using System-Verilog OVM/UVM, reusable bench environment for sub system and full chip level. Developing test plans, writing and running test using constrained random ... - 2017 Mar 15
Electrical Engineer Power Plant
Fremont, CA
... CA-94536 Mobile: +1-669-***-**** I AM CURRENTLY SEEKING AN OPPORTUNITY IN FIELD OF ASIC DESIGN OR VERIFCATION SKILLS: Technical skills: RTL-design, ASIC verification, Verilog, FPGA, C-programming, Testing, Networking (Routing and switching) . ... - 2017 Mar 14
... CA-94536 Mobile: +1-669-***-**** I AM CURRENTLY SEEKING AN OPPORTUNITY IN FIELD OF ASIC DESIGN OR VERIFCATION SKILLS: Technical skills: RTL-design, ASIC verification, Verilog, FPGA, C-programming, Testing, Networking (Routing and switching) . ... - 2017 Mar 14
Actively seeking full time position as a Physical Design Engineer
San Jose, CA
... India July’11 SKILLS CAD(EDA) Tools Synopsys VCS, Cadence Virtuoso IC Design suite, Spectre, IC Compiler, HSpice Skills Synthesis, RTL simulation, Logic Design, DRC, LVS, Physical Design, Schematic, Lynx Flow Languages Verilog, tcl/tk, C. ... - 2017 Mar 09
... India July’11 SKILLS CAD(EDA) Tools Synopsys VCS, Cadence Virtuoso IC Design suite, Spectre, IC Compiler, HSpice Skills Synthesis, RTL simulation, Logic Design, DRC, LVS, Physical Design, Schematic, Lynx Flow Languages Verilog, tcl/tk, C. ... - 2017 Mar 09
Physical Design Full Time
San Jose, CA
... with EDA tools: Cadence Virtuoso, DC, IC Compiler, PrimeTime, Verdi, VCS, DVE, ModelSim, etc • Experienced with Verilog, SystemVerilog, VHDL, scripting languages Perl • Knowledge of ASIC/SoC Design/Verification flow • Knowledge of computer ... - 2017 Mar 02
... with EDA tools: Cadence Virtuoso, DC, IC Compiler, PrimeTime, Verdi, VCS, DVE, ModelSim, etc • Experienced with Verilog, SystemVerilog, VHDL, scripting languages Perl • Knowledge of ASIC/SoC Design/Verification flow • Knowledge of computer ... - 2017 Mar 02
Design Electrical Engineering
Sunnyvale, CA
... and Communication 09/2007 – 06/2011 PES Institute of Technology, Bengaluru, India GPA: 8.12/10.00 Skill Set Language : C, C++, Verilog, VHDL, System Verilog, Perl, TCL, HSpice Software & IDEs : Cadence – Virtuoso, Encounter, Assura, Quantus RC; ... - 2017 Mar 01
... and Communication 09/2007 – 06/2011 PES Institute of Technology, Bengaluru, India GPA: 8.12/10.00 Skill Set Language : C, C++, Verilog, VHDL, System Verilog, Perl, TCL, HSpice Software & IDEs : Cadence – Virtuoso, Encounter, Assura, Quantus RC; ... - 2017 Mar 01
Design Engineer Technical
Santa Clara, CA
... Development and verification of the CHACE-II design in verilog. Technical and test report preparation of the work describing the software and hardware requirement. EDUCATION Amrita Viswa Vidyapeetham, Kerala, India GPA: 8.08/10 Master of Technology ... - 2017 Mar 01
... Development and verification of the CHACE-II design in verilog. Technical and test report preparation of the work describing the software and hardware requirement. EDUCATION Amrita Viswa Vidyapeetham, Kerala, India GPA: 8.08/10 Master of Technology ... - 2017 Mar 01