Neilson Yi-Ying Cheng

**** ***** *****, *** ****, CA 95131 405-***-**** aczb9f@r.postjobfree.com

Objective:

Seeking for fulltime entry level NCG position as: Analog Design Engineer, Mixed Signal Design Engineer, RFIC Design Engineer.

Also available for an Associate Engineer; paid or unpaid.

Preferred locations not limited to: San Jose, Sunnyvale, Santa Clara, Milpitas, Mountain View, Palo Alto, San Francisco, Seattle, Austin, Dallas.

Open to relocation with minimal assistance needed.

Available to work immediately for any USA employers with valid EAD card.

Education:

MSEE, Masters of Science in Electrical Engineering.

UCLA, University of California, Los Angeles, CA. Graduated Fall 2016.

BSEE, Bachelor of Science in Electrical Engineering.

Tamkang University, New Taipei City, Taiwan. Graduated 2010

Awards and Scholarships:

3rd Place Award in 2010 IC Full Custom Digital Circuit Design Competition, Hsinchu, Taiwan. 2010

Taiwan NSC College Student Participating Special Project Scholarship, Taipei, Taiwan. 2009

Skills:

Electronic Measurement: oscilloscope, probe station

Design and Simulation Tools: Cadence Virtuoso, HSPICE, CPPsim, LTspice, EasyEDA, Eagle, Modelsim

Software design and analysis: MATLAB, C/C++, Verilog, VHDL, Visual Basic, Office

Internship and Research Experience:

Research Assistant, Integrated Bioelectronics Research Lab at UCLA; Prof. Wen-Tai Liu. 2015-2016

Designed Analog Front End for Fast Scan Cyclic Voltammetry (FSCV) with 10pA input-referred current noise and 3μ W power consumption in 65nm process.

Formulated Transcutaneous Electrical Nerve Stimulator (TENS) to achieve 20% lower edge effects, and designed on-broad power management with adjustable high power output.

Intern, Hycon Technology (Testing engineer for high-precision measurement system). 2014

Constructed test-bench and measured conversion efficiency of charge pump and Effective Number of Bits (ENOB) of ΔΣ ADC on customized software.

Evaluated specifications of individual analog IPs (e.g. LDO, Bandgap Reference, Oscillator and ΔΣ ADC) for integration in commercial product.

Research Assistant, Tamkang University Department of Electrical Engineering. 2014

Designed and verified a 12-bit, 50M Hz Wideband Multi-Channel ΔΣ Modulator, and optimized performance tradeoff based on different system architectures.

Academic Projects:

Low power 10-bit current steering DAC in 45nm process (Analog Microsystems Design). 2016

Reduced power dissipation by analyzing the trade-off between output impedance of current cell and SFDR

Achieved 9.76-bit ENOB, 60dB SFDR at 1GS/s, DNL and INL of less than 1 LSB.

Low-Noise Amplifier (LNA) for LTE band Ι in 90nm process (Analysis and Design of RF Circuits and System). 2016

Designed using cascode topology and inductor degeneration to reach S11 -11dB @ 2.11G Hz, IIP3 -1.77 dBm, and Noise Figure < 1.1 dB, and 1.8m W power consumption through entire LTE Ι band.

Electromyography (EMG) Decomposition Algorithm for neural recordings. 2015

Implemented Principle Component Analysis (PCA) methods for neural signal decomposition and analysis.

Fractional-N PLL with ΔΣ modulator in 45 nm process (Signaling and Synchronization, VLSI Circuits & Systems). 2015

Constructed a nested PLL model and analyzed the system stability simulation to suppress phase noise < -90 dBc/Hz at 1M Hz offset; designed a ring oscillator with -110 dBc/Hz phase noise at 1M Hz frequency offset.

64Kb Content-Addressable Memory in 45 nm process (Digital Integrated Circuit Design). 2015

Optimized critical delay path to achieve search time of 0.33 nanosecond.

Fully-Differential High-Precision Amplifier in 180 nm process (Analog Integrated Circuit Design). 2014

Incorporated a folded-cascode topology with CMFB to achieve gain of 64 dB, phase margin 63, bandwidth 350M Hz, 125 microsecond settling time, and 0.7% steady state error.

Undergraduate Thesis. 2009-2010

Low Power SAR ADC for Electrocardiogram in 350 nm CMOS process

Evaluated performance at multiple levels (MATLAB, HSPICE, and Cadence Virtuoso).

Implemented physical layout and achieved 9.2 bit resolution with 25μ W power consumption.

Keywords:

ADC, DAC, PLL, OpAmp, IC, VLSI, High-tech, Engineering, Hardware, Bay Area, Startup

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