Physical Design Full Time

GuopengWang

**** ********* *** ****: 213-***-****

San Jose, CA, 95128 Email:*******.******@*****.*** Objective

Full time position in ASIC/SoC Verification/Physical Design or related position Core Qualification

• Experienced with physical design and complete flow

• Experienced with EDA tools: Cadence Virtuoso, DC, IC Compiler, PrimeTime, Verdi, VCS, DVE, ModelSim, etc

• Experienced with Verilog, SystemVerilog, VHDL, scripting languages Perl

• Knowledge of ASIC/SoC Design/Verification flow

• Knowledge of computer architecture, Tomasulo, cache coherency, MOESI, FIFO

• Highly motivated team worker with efficient self-learning and problem-solving abilities Work Experience

Oracle, Santa Clara, CA

Hardware Developer Feb. 2014 – Now

• Work in SoC physical design team, experienced whole flow from RTL to GDSII.

• Experience with 16nm, 10nm technology and high frequency >= 2.5Ghz design.

• Responsible for floorplan optimization, CBs logic synthesis, custom datapaths placement, LEC, clock and power distribution, place and route.

• Work closely with RTL team to re-code RTL for physical design needs.

• Work closely with Timing team to help develop and debug timing flow.

• Work closely with CAD team in testing and developing optimized flows for new technologies

• Develop scripts to optimize physical design flow to solve both routing and timing problems Academic Projects

1 k-bit SRAM design

- Design 1k-bit SRAM with four banks, together with CLA to design a noise attenuation chip. The whole schematic and layout are drawn manually. Tomasulo processor design

- Write code in VHDL, simulate and verify in ModelSim, synthesized by Xilinx and implement on the Spartan6 FPGA board. Learn details of Tomasulo such as Dispatch, Issue Queue, PRF. Education

University of Southern California Aug. 2012 - Dec. 2013 MS in EE general Major GPA: 3.8/4.0

Courses: Computer Organization/Architecture, VLSI System Design, Digital System Design University of Electronic Science&Technology of China Sept. 2008 - June. 2012 Major in Microelectronic Technology GPA: 3.5/4.0

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