RANJANA AJAYAKUMAR

*** ******** ******, *** **, Santa Clara, 95050

Phone: 408-***-**** Email: acy2ho@r.postjobfree.com WORK EXPERIENCE 2 years

Vikram Sarabhai Space Center (VSSC), ISRO, India July 2014 - August 2016 Design Engineer

Hardware and firmware development of the onboard controller of RAMBHA (Radio Anatomy for Moon Bound Hypersensitive ionosphere and Atmosphere) and CHACE-II

(Chandras Altitudinal Composition Explorer) payload for the Chandrayaan-II mission of ISRO at VSSC.

Designed the schematics for a space qualified DSP based onboard controller and spacecraft interface system for RAMBHA.

Designed the schematics for a FPGA based onboard controller for CHACE-II.

Functionally verified and performed the OrCAD schematic design rule checks for both the designs.

Selection of the space qualified parts based on dimension, weight and package.

Developed the assembly language code for data acquisition, telecommand transmission and telemetry reception for RAMBHA.

Development and verification of the CHACE-II design in verilog.

Technical and test report preparation of the work describing the software and hardware requirement.

EDUCATION

Amrita Viswa Vidyapeetham, Kerala, India GPA: 8.08/10 Master of Technology in VLSI Design - August 2014

Amrita Viswa Vidyapeetham, Kerala, India GPA: 7.66/10 Bachelor of Technology in Electronics and Communication –September 2012 COURSE PROJECTS

Designed and implemented a reconfigurable custom processor in Verilog .This project focussed on the design of a Custom processor with design portability and programmable bus width and register sizes. The processor incorporates several additional features like DMA capability, Interrupt controller, Effective peripheral interfacing and half word select option.

A protocol for expeditious error reconciliation in Quantum Key Distribution (QKD) systems for FPGA compatible devices was implemented in Verilog.

Designed Single cycle, Multicycle and Pipelined architectures of Microprocessor without Interlock Pipeline Stages (MIPS) CPU in Verilog. Compared the speed of the three architectures using Xilinx ISE 10.1 FPGA.

A smart card based home security system using PIC microcontroller was implemented. PIC16F877A microcontroller was used and the design was developed in MPLAB.

PUBLICATION

S.Anu, Ranjana Ajayakumar, Ramesh Bhakthavatchalu, P.Pradeepkumar “Reconfigurable Custom Processor Design in FPGA” International Conference on Communication and Computing, ICC-2014, vol. 3. Elsevier, Bangalore, India, pp. 66-74, 2014. TECHNICAL SKILLS

Tools : Libero SoC, Modelsim, CCS, OrCAD, Matlab, MPLAB, Cadence Virtuoso. Languages : Verilog, Assembly

VISA STATUS

On H4B VISA with EAD (Work Authorization).