JAGANNATHAN RADHAKRISHNAN

(R) 408-***-**** (C) 408-***-**** aczbto@r.postjobfree.com

Experienced Verification/Designer of ASIC/FPGA, SOC for telecom and computer industries.

SUMMARY OF QUALIFICATIONS

Over 15 years of System design, SOC, ASIC/FPGA design, Modeling and Verification background.

Experience in understanding and implementing ITU (Telecom), Storage (AHCI/SATA/eMMC & NVME/SOP/PQI over PCIe) standards & SRIOV

Experience in understanding and implementing ONFI/TOGGLE NAND I/F standards & worked on SLC/MLC and TLC NANDs

Implemented UPF based low power methodology for client SSD drive

Effective communication and interpersonal skills.

Good leadership and Proactive team player.

ACHIEVEMENTS

Implemented a protocol-based solution for achieving 5-year battery life for the wireless based Electronic Shelf Label, which has gained the retail market segment significantly.

Successfully taped out multiple chips.

Star Performer Award for making the ASIC to work at First Silicon.

PROFESSIONAL SKILLS

System verilog RTL programming in wide variety of projects

Working knowledge of Xilinx and Altera FPGA design methodologies

Working knowledge of PCIe/eMMC/SATA/SCSI and DDR2/GDDR LPDDR3/4 protocols

Working knowledge of low power design methodologies

Working knowledge on VMM and UVM methodologies

Professional Experience:

NXP Semiconductors (Aug 2016 – Till date)

R&D Engineer (IoT/Security/Low Power Micro Controllers)

Implemented adaptive replacement policy for cache controller (Between ARM & Flash memory)

Owned UVM based IP level as well as full chip verification environment to verify Cache controller

Implemented & Integrated PRINCE on the Fly Encryption & Decryption mechanism & Verified at full chip level

Integrated and verified low cost AES engine at full chip level

SK Hynix Memory solutions (Aug 2013 – Aug 2016)

Principal Engineer (LPDDR3/4 Performance simulation & NAND die model & SATA Host subsystem env)

Implemented UVM based subsystem verification env. for SATA and ATA power management function verification & error injection and recovery handling mechanism.

Architected and implemented NAND die model (SystemVerilog) (Functional, timing check and command sequence check)

Worked on test firmware in C++ and Systemverilog for measuring H/W performance that includes adding functional cover groups, assertions and monitors at various data paths and control paths to measure the latency and throughput for Sequential writes, Random reads to NAND Flash

Implemented Performance centric NAND commands like ONESHOT program, CACHE commands, Internal move, Erase suspend and few others

Verification of FTL

Worked on LPDDR3/4 block verification in UVM & helped to port to full chip verification.

Participated in UVM based block level verification env. For Command Q and DMA I/F of FTL

Implemented assertions and functional cover groups methodology (SystemVerilog)

Verification architecture for the entire SoC & Responsible for complete testplan execution

Worked on UPF low power methodology (Verification infrastructure, UPF script, SATA power management commands & LPDDR3/4 low power verification)

Link-a-Media Devices corporation, Santa Clara, CA (HDD/SSD Controller)

Sr. Staff Engineer, (Architecture/verification team) Oct 2009 - Aug 2013)

Next generation SoC for SSD (Enterprise/Desktop application)

Application layer (AHCI, NVM Express/SOP and PQI)

Built the verification env. For AHCI, NVME/SOP/PQI over PCIE in VMM (Includes Xactor, TLMs, scoreboards and drivers)

Implemented SRIOV for both NVME and SOP on PCIE (VMM based application layer)

Implemented UPF based low power design & verification methodology

Responsible for Register level F/W function development

Co-ordinated with OEMs for Host F/W development (SOP/PQI)

Verification Architecture for Host controller (PCIe/SATA/eMMC)

H/W acceleration for Host controller I/F.

CPF based Low power methodology for static power saving

C++ library development for simulation of SoC at System level

Architecture for VMM based SATA BFM (Using Denali VIP) & PCIe Application layer

Integrated VMM based scoreboard for verifying AES encryption/decryption (SATA)

Responsible for DSM (ARM) flow verification of SoC

Responsible for GATE level simulation/Functional coverage

Key achievement: Design wins from various customers (Units are at OEMs now for evaluation!)

Verification Architecture for Hybrid SoC (SSD Cache for HDD controller)

Verified DDR2 Slave I/F for caching HDD traffic

Lead VMM based BFM for block level verification environment

Implemented DSM verification flow for HDD SoC and Hybrid SoC combined environment

Defined F/W later at command I/F (HDD F/W to Hybrid SoC F/W)

Implemented boot ROM code for the Hybrid SoC

Co-ordinated with TOSHIBA for the entire duration of ASIC development

Responsible for GATE level simulation/Functional coverage

Key achievement: Hybrid product has been scheduled by TOSHIBA for customer evaluation!

ALTIERRE corporation designs and develops a complete System solution to Retail industries, based on RFID technology to do dynamic price update and store operations.

Staff Engineer/Architect, ALTIERRE Corp, San Jose, CA (July 2008 – April 2009)

Architecture of next generation Access point for dynamic pricing solution, based on proprietary wireless technology, targeted on Xilinx FPGA

Architected a proprietary protocol based low power design methodology for wireless based ESL.

Micro architecture and RTL Implementation of TDMA based MAC/Scheduler & PHY for the wireless access point in Verilog.

Implemented closed loop digital control system for RF & digital board monitoring, interfacing to 8 Channel ADC (TLV1508) and digital PLL & Synthesizers – thro’ serial parallel interface.

Mapping Base Band algorithm from MATLAB into Synthesizable Verilog RTL, targeted to Spartan 3 FPGA.

Complete integration of Base Band into PHY and MAC/LINK layers.

Proposed a new architecture for a cost effective access point based on RTOS and Interrupt driven S/W

Lead the complete Access Point system development on Xilinx FPGA Platform.

Lead the prototype system bring up team in the LAB

Key achievement: Gained 5+ years of battery life for the ESL!

Advanced Micro Devcies Inc. (CPU/GPU and chipset design and development

Staff Design Engineer, AMD, Santa Clara, CA (July 2007 – July 2008)

Developed High-level TLM System Model (Verilog, System C/PLI interface) for the Memory controller.

Verification of GDDR2/3/4/5 Memory controller for Advanced Graphics Chipset (SOC)

Key achievement: Gained more than 98% functional coverage by uncovering the corner cases!

EXAR Corporation. (Design and develops telcom ASICs – PHY and Layer1 chips)

Staff Design Engineer, EXAR Corp. FREMONT, CA (July 2000 – July 2007)

(Leading the architecture, design & verification)

Design and Development of scalable VCAT/LCAS IP Core for Ethernet Over Sonet and Ethernet Over PDH series of products for telecommunication network.

Architecture definition, Design and implementation of Source VCAT/LCAS IP from specification to Silicon

RTL Verification of Source and Sink VCAT/LCAS function, Silicon bring up in the Lab

Key achievement: Silicon was proven at the first tape out!

Design and Development of SPI-4 Link Interface for OC192 Mapper / Demapper.

Architecture definition, Design and implementation of SPI-4 TX and RX IP core in VERILOG – From specification to Silicon

Performed Synthesis and Static Timing Analysis

Developed VERILOG models and system level test bench

Developed Digital Data Eye core and verification environment in VERILOG for SPI-4 TX interface for dynamic data alignment

Key achievement: Prototype was proven in Xilinx Platform (>95% of functionality)

Member of Technical staff, Sun Microsystems Inc. Menlo Park, CA (Sep 1999 – July 2000)

Verification of Frame Buffer Controller and Graphics Controller at system level in C and C++ language

Member of Technical staff, Integrated Intellectual Property Inc. Santa Clara, CA.

Contracted at the following places.

PHILIPS Semiconductors. Sunnyvale, CA (May 1999 – July 1999) – (Contract Position)

Verification of MIPS Processor core using C and assembly language

FORE Systems Inc. San Jose, CA (Feb 1998 – Feb 1999) – (Contract Position)

Verification of 10/100 MBPS Ethernet MAC ASIC at system level

Education:

MSEE (VLSI Design, DSP and Computer architecture)

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