DUNG NGUYEN

Phone: 408-***-****

Email: acza8n@r.postjobfree.com

OBJECTIVE: Looking for position in Design Verification Engineer.

QUALIFICATIONS: Specializations including verification, developing test bench using System-Verilog OVM/UVM, reusable bench environment for sub system and full chip level. Developing test plans, writing and running test using constrained random variable, developing, debugging test, collecting and close coverage.

Development test bench component: BFMs, Monitors, Checkers, agent, Scoreboard, reusable testbench component, direct and constrained random test suit, checkers, trackers. Including functional coverage, code coverage, and assertion methodology using SystemVerilog, Verilog, C++ object oriented, System-Verilog OVM/UVM and writing assembly test.

Involving test plan creating, execution, writing test (also stimulus for corner case), debugging, driving bug closure using VCS verification tool. Using C++ object oriented (System Verilog) to generate testbench data.

Experience with assertion driven validation. Development of functional coverage groups/points to achieve coverage goals (also for corner case). Writing SVA (assertion) as a part of function coverage.

Running regression, debugging test fail, review waveform to find root cause. Improving number of test pass.

Using Perl script, C shell for test bench automation and creating environment component. Partition checker module, also making test bench environment suitable for test reusable purpose.

Able to work well, excellent communication skill as team member as well as effectively cross-function with other teams. As well as interfacing with emulation and software teams. Experience with tool development and tool integration.

Hardworking, detail oriented, under pressure. Strong discipline and attention to detail in ensuring effective high quality validation that minimizes bug escapes.

TECHNICAL SKILL

Implement, developing verification infrastructure: reference model, direct, random test, coverage model, transactors and other bench component.

Using the assertion (from System Verilog) to check the bus protocol. Enabling and bring up coverage.

Running and debug testbench using VCS. Using Verdi to bring up waveforms during rtl module debugging.

Writing script (c-shell, Perl) for compiling test before running, automate generating testbench module for test reusable and checking output of log file result to determine which tests pass or fail.

Proficient in System Verilog (class object oriented, data structure, random variable, assertion, interface, coverpoint), formal verification, Synopsys VCS, Debussy, Modelsim, C++, c-shell Mentor, Cadence simulation tool, Specman, OVM/UVM, AHB, AXI SOC bus protocol, PCIE express, CPU architecture, SOC component, DPI, Perl for creating environment module and test bench automation, Unix, Assembly Language, Altera Quartus II, Unix shell, Jasper Gold. Python. SVN, revision control. I2C, SPI, UART, GPIO.

WORK EXPERIENCE

INTEL SDG group Santa Clara, CA OCT 2016 - DEC 2016

Design verification Engineer

Creating test, running regression, debugging, collecting coverage, improving test bench environment.

INTEL PEG group Folsom, CA SEP 2014 - MAY 2016

Design verification Engineer

Responsible for creating test bench infrastructure, stimulus generator, monitor, checker, debugging and ramping up test (improve number of test pass) and run weekly regression, emulation (FPGA) and UPF, manage bug tracking, performance verification for latest SOC Cannon Lake CPU and pcie sub system.

Base on architecture spec to come up with test plan, random test generation. Developing both direct, constrained random test case. Also writing test stimulus using C++, assembly.

Developing test suite using system verilog, OVM/UVM, stargate for concurrency, aperture: IA, OPI test according to test plan. Concurrency working with rtl team, DA team to improve number of test pass.

Implement, creating bench infrastructures: transactors, checker, monitor and reference model.

Creating, enabling, collecting and analysis coverage (code and function) for all related IA, GT test. Working with rtl team to improving coverage based on weekly basic and verify the correctness of the design.

Enabling an OPI test flow (which define main traffic from PCH from south bridge to main CPU), gtpm, aperture test and concurrency test flow (using system verilog and OVM) to verify difference CPU feature.

Creating new reference model, with new feature add in for each rtl miles stone, validate them during weekly regression. Working with GT team, running, debugging test fail to improve number of test pass.

Working with post Silicon team for silicon bring up and debug. Developing script using perl for automation.

Broadcom BCG group Santa Clara, CA DEC 2011 – Dec 2013

Design verification Engineer

Working on formal verification, evaluate C++ modeling (using systemC) for the next generation Broadcom ultraHD 4K video chip (BCM7445 based on ARM A15 architecture).

Using constraint random variable (SystemVerilog, OVM, UVM) to generate data structure input based on picture size, resolution.

Using Jasper tool (formal verification) to create a driver which utilizes an AXI bus protocol. Also writing a list of assertion (System Verilog) to check if the communicate between driver and DUT follows AXI bus protocol.

Involve building C++ model and BFM using System Verilog. Write a scoreboard, to verify correctness output from rtl module during running regression.

Creating cover point (System Verilog, OVM, UVM) for function coverage. Create test suite for AXI (AMBA) bus transaction using assemble language. Debugging test failure, running regression by using these direct test and random test.

Writing environment files including Makefile, Perl script used to generate output expected data file, test configuration file and register value data file which used to initialize list of register for rtl module under test.

Debugging test fail by using Verdi, bringing up waveform to determine behavior, expected data from the rtl.

Partition checker module into general portions so that they can be reusable to verify for other IPs (DUT) module. Including upstream, downstream checker for the ARM bridge and another checker for slave.

Developing C-shell script for auto generated partition checker module code. Goal is creating auto generate checker module for each IPs module for reusable purpose.

Intel Intern ECG Group Chandler, AZ JUNE 2011 - DEC 2011

Design Component (verification) Engineer (WWID 11376359)

Working on nCPM project (Pre Silicon) which is derivative from the Cave Creek project. nCPM is integrated into Avaton.

Understand nCPM architecture, block function, and IOSF protocol.

Debug regression test (C++ test based from Cave Creek regression test suite) related to Micro Engine (one of the Master inside nCPM)

Modify and analyzing coverage, monitors, event injectors, architectural and micro-architectural correctness checkers as well as test content and test plan using Proto and OVM / UVM System Verilog.

SPANSION (AMD) LLC Sunnyvale, CA 2003-2009

Test, Product Verification Engineer

Validation, characterize, qualification SPANSION parts based on the specific customer system requirement.

Customer failure analysis: Worked with customer on their system level to determine how SPANSION (NAND/NOR) part failed on customer system. Determine the failure mode and giving customer advice for corrective action.

Performance analysis: Characterized competitor part in terms of performance, function.

EDUCATION

San Jose State University, San Jose, CA FEB 2010 - MAY 2014

M.S.E in Electrical Engineer

Relevant Course Work:

1.Digital Design for DSP & Communications (FPGA) using ISE design suit and Quartus II Projects

2.SoC Design and Verification with System Verilog using the AMBA bus for ARM Projects

3.Digital System Design and Synthesis Project

University Of Sana Cruz Extension, Santa Clara, CA FEB 2010 – DEC 2010

Embedded Systems Certificate

Relevant Course :

PCI, PCI-X, PCIE ( gen 2, gen 3 ), DMA, Interrupts, ethenet, fibre Channel, Network, Switch ...

University Of Michigan, Ann Arbor, MI Graduation: MAY 2003

B.S.E Electrical Engineer

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