| Resume alert | Resumes 131 - 140 of 448 |
Design Electrical Engineering
Santa Clara, CA
... DSCE, Bangalore (80.34 %) June 2015 Bachelor of Engineering in Electronics and Communication TECHNICAL & SOFTWARE SKILLS Verilog, SystemVerilog (Mailboxes, Queues, Virtual Interfaces, Assertions, Semaphores, Randomised Constraints, Covergroups), ... - 2017 Aug 18
... DSCE, Bangalore (80.34 %) June 2015 Bachelor of Engineering in Electronics and Communication TECHNICAL & SOFTWARE SKILLS Verilog, SystemVerilog (Mailboxes, Queues, Virtual Interfaces, Assertions, Semaphores, Randomised Constraints, Covergroups), ... - 2017 Aug 18
Physical Design engineer
Palo Alto, CA
... Languages: Skill, TCL, RTL, VHDL, Verilog, SystemC, SystemVerilog, Perl, Python, C, C++, CUDA, MPI, OpenMP, Pthread, Bash, Matlab. Computer Architecture Software and Compilers: GNU (gcc, g++, gdb, gcov), Gem5, Valgrind, Windows-COM, Git. Network ... - 2017 Aug 14
... Languages: Skill, TCL, RTL, VHDL, Verilog, SystemC, SystemVerilog, Perl, Python, C, C++, CUDA, MPI, OpenMP, Pthread, Bash, Matlab. Computer Architecture Software and Compilers: GNU (gcc, g++, gdb, gcov), Gem5, Valgrind, Windows-COM, Git. Network ... - 2017 Aug 14
Masters of Science
San Jose, CA
... Education MASTERS IN ELECTRICAL ENGIEERING (THESIS) MAY 2017 UNIVERSITY OF HOUSTON GPA: 3.85/4 BACHELORS IN ELECTRONICS AND COMMUNICATION ENGINEERING JUNE 2015 VTU, INDIA GPA: 3.8/4 Technical Skills Programming: C, MATLAB, Verilog, VHDL, Python, ... - 2017 Aug 11
... Education MASTERS IN ELECTRICAL ENGIEERING (THESIS) MAY 2017 UNIVERSITY OF HOUSTON GPA: 3.85/4 BACHELORS IN ELECTRONICS AND COMMUNICATION ENGINEERING JUNE 2015 VTU, INDIA GPA: 3.8/4 Technical Skills Programming: C, MATLAB, Verilog, VHDL, Python, ... - 2017 Aug 11
Design Electrical Engineering
Newark, CA, 94560
... TECHNICAL SKILLS HDL: Verilog, VHDL, System Verilog (OVM & UVM methodologies). Scripting: Perl. EDA Tools: Cadence RTL compiler, Synopsys Design compiler, IC compiler, TetraMax, DFT, BSD. Programming Languages: C, C++. Others: HSPICE, IRSIM, Magic ... - 2017 Aug 10
... TECHNICAL SKILLS HDL: Verilog, VHDL, System Verilog (OVM & UVM methodologies). Scripting: Perl. EDA Tools: Cadence RTL compiler, Synopsys Design compiler, IC compiler, TetraMax, DFT, BSD. Programming Languages: C, C++. Others: HSPICE, IRSIM, Magic ... - 2017 Aug 10
Engineer Network
Fremont, CA
... Hsinchu, Taiwan (R.O.C) Digital Hardware engineer: I served in the R&D division, where I was responsible for writing digital circuit cell phone drivers using Verilog. - 2017 Aug 05
... Hsinchu, Taiwan (R.O.C) Digital Hardware engineer: I served in the R&D division, where I was responsible for writing digital circuit cell phone drivers using Verilog. - 2017 Aug 05
Design Test
Santa Clara, CA
... Technical Intern (IoT Team), Renesas Electronics ( Santa Clara, CA ) July 2017- Present Developed python script to parse the Verilog netlist file and return total number of modules in Topcell hierarchy Circuit Simulation R&D intern Intern, Ansys ( ... - 2017 Aug 02
... Technical Intern (IoT Team), Renesas Electronics ( Santa Clara, CA ) July 2017- Present Developed python script to parse the Verilog netlist file and return total number of modules in Topcell hierarchy Circuit Simulation R&D intern Intern, Ansys ( ... - 2017 Aug 02
Customer Service Java Developer
Fremont, CA
... closely with hardware and electrical team Programming: Core Java, C#, C, C++, JavaScript, PHP, XML, SQL, MySQL, VB.NET, Scala, Verilog, Arduino, CSS, SQL, Html, Equipment: Circuit board prototyping, Semiconductor Tools Education and Honor Relevant ... - 2017 Jul 20
... closely with hardware and electrical team Programming: Core Java, C#, C, C++, JavaScript, PHP, XML, SQL, MySQL, VB.NET, Scala, Verilog, Arduino, CSS, SQL, Html, Equipment: Circuit board prototyping, Semiconductor Tools Education and Honor Relevant ... - 2017 Jul 20
C,C++, Verilog, Python
San Jose, CA
... TECHNICAL SKILLS Programming languages: Verilog HDL, C and C++, Embedded C, Python. EDA Tools: Synopsys VCS, Design Compiler, Design Vision, Keil. Soft Skills: Self Motivated, Team Player, Effective Communication Skills, Adaptable to work ... - 2017 Jul 07
... TECHNICAL SKILLS Programming languages: Verilog HDL, C and C++, Embedded C, Python. EDA Tools: Synopsys VCS, Design Compiler, Design Vision, Keil. Soft Skills: Self Motivated, Team Player, Effective Communication Skills, Adaptable to work ... - 2017 Jul 07
VLSI Digital Design Engineer
Santa Clara, CA
... VHDL/Verilog Design, Implementation and Synthesis on both Altera and Xilinx Platform. Verilog synthesis, placement and routing and debugging using Synopsys VCS and analysis using design vision. WORK EXPERIENCE: COTMAC ELECTRONICS PVT.LTD. - Intern ... - 2017 Jul 03
... VHDL/Verilog Design, Implementation and Synthesis on both Altera and Xilinx Platform. Verilog synthesis, placement and routing and debugging using Synopsys VCS and analysis using design vision. WORK EXPERIENCE: COTMAC ELECTRONICS PVT.LTD. - Intern ... - 2017 Jul 03
Design Engineer
San Jose, CA
... in developing Reconfigurable software with reconfigurable Hardware on FPGA where we designed a multiplayer game using Verilog HDL on Xilinx Vivado and C++ to develop GUI for communication between FPGA board and PC Guru Gobind Singh Indraprastha ... - 2017 Jul 03
... in developing Reconfigurable software with reconfigurable Hardware on FPGA where we designed a multiplayer game using Verilog HDL on Xilinx Vivado and C++ to develop GUI for communication between FPGA board and PC Guru Gobind Singh Indraprastha ... - 2017 Jul 03